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1. 发明授权

US08872279B2 Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one another 有权
标题翻译：晶体管结构具有电接触结构，多个金属互连层互相交错
公开(公告)号：US08872279B2
公开(公告)日：2014-10-28
申请号：US13347851
申请日：2012-01-11
申请人： David R. Greenberg , Jean-Olivier Plouchart , Alberto Valdes-Garcia
发明人： David R. Greenberg , Jean-Olivier Plouchart , Alberto Valdes-Garcia
IPC分类号： H01L27/088 , H01L23/482 , H01L29/423 , H01L29/78
CPC分类号： H01L27/0207 , H01L23/4824 , H01L23/528 , H01L27/088 , H01L29/41758 , H01L29/42376 , H01L29/4238 , H01L29/78 , H01L2924/0002 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
摘要翻译：电接触结构沿其长度分布电流。电接触结构包括在n级金属上的多个n个金属矩形。一个金属层上的矩形至少具有宽度的宽度，并且垂直地在宽度上覆盖紧接在下面的金属层上的矩形。一个金属层上的矩形长度短于第一端，并且在紧靠下方的金属层上的矩形基本对齐。矩形的第一端基本对齐。本发明的示例性FET晶体管的特征是源极和漏极端子电接触结构，在两端连接栅极矩形的多级金属环和大于最小栅极至栅极间隔。本发明例如在电迁移兼容的高性能晶体管中是有用的。

2. 发明申请

US20120112309A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION 有权
标题翻译：具有后续自对准的双盒式背盖的低成本制造硅绝缘体波纹
公开(公告)号：US20120112309A1
公开(公告)日：2012-05-10
申请号：US13350889
申请日：2012-01-16
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/76275 , H01L21/76283 , H01L27/1203
摘要： A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.
摘要翻译：用于制造集成电路器件的半导体衬底结构包括块状衬底; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在下绝缘层上的导电层; 在所述导电层上形成具有蚀刻停止特性的绝缘体; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。还公开了一种随后构建双深度浅沟槽隔离的方案，其中在与这种半导体衬底中的有源区域中较浅的STI自对准的背栅层中的较深STI相比较。

3. 发明申请

US20100176453A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER 失效
公开(公告)号：US20100176453A1
公开(公告)日：2010-07-15
申请号：US12352071
申请日：2009-01-12
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L29/78 , H01L23/58 , H01L21/30
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/78648
摘要： A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

4. 发明申请

US20080124881A1 INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR Si-Ge BIPOLAR TECHNOLOGY 失效
标题翻译：加入硅/硅锗外延层加强Si-Ge Bipolar技术的加强
公开(公告)号：US20080124881A1
公开(公告)日：2008-05-29
申请号：US11562735
申请日：2006-11-22
申请人： Jack Ooh Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
发明人： Jack Ooh Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/02447 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/1004 , H01L29/161 , H01L29/7378
摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
摘要翻译：提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

5. 发明授权

US07767546B1 Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer 失效
标题翻译：低成本制造双盒背栅硅绝缘体晶片，在背栅层中内置浅沟槽隔离
公开(公告)号：US07767546B1
公开(公告)日：2010-08-03
申请号：US12352071
申请日：2009-01-12
申请人： Robert H. Dennard , David R. Greenberg , Amian Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amian Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L21/30
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/78648
摘要： A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.
摘要翻译：用于制造集成电路器件的半导体晶片结构包括体基片; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在所述下绝缘层上的导电层，所述导电层还具有形成在其中的一个或多个浅沟槽隔离（STI）区域; 形成在所述导电层和所述一个或多个STI区域上的蚀刻停止层; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。还公开了随后的有源面积电平STI方案，结合半导体层上的前栅极形成。

6. 发明授权

US07642569B2 Transistor structure with minimized parasitics and method of fabricating the same 有权
标题翻译：具有最小化寄生效应的晶体管结构及其制造方法
公开(公告)号：US07642569B2
公开(公告)日：2010-01-05
申请号：US12366425
申请日：2009-02-05
申请人： David R. Greenberg , Shwu-Jen Jeng
发明人： David R. Greenberg , Shwu-Jen Jeng
IPC分类号： H01L29/737
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/0821 , H01L29/42308 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.
摘要翻译：提供了具有最小化寄生效应的晶体管，其包括在本征发射极部分顶部具有凹入的非本征发射极部分的发射极; 包括与本征发射极部分电接触的本征基极部分的基极和与本征基极部分电接触并且通过一组发射极/基底间隔物与凹入的非本征发射极部分电隔离的非本征基极部分; 以及与本征基部电接触的集电体。晶体管可以进一步包括具有完全硅化到发射极/基极间隔物的顶表面的外在基极。另外，晶体管可以包括在晶体管的有效区域内的基极窗口。还提供了形成上述晶体管的方法。

7. 发明授权

US07425754B2 Structure and method of self-aligned bipolar transistor having tapered collector 有权
标题翻译：具有锥形集电极的自对准双极晶体管的结构和方法
公开(公告)号：US07425754B2
公开(公告)日：2008-09-16
申请号：US10708340
申请日：2004-02-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
IPC分类号： H01L27/102
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.
摘要翻译：提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积下表面。双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

8. 发明授权

US07355221B2 Field effect transistor having an asymmetrically stressed channel region 有权
标题翻译：具有不对称应力通道区域的场效应晶体管
公开(公告)号：US07355221B2
公开(公告)日：2008-04-08
申请号：US10908448
申请日：2005-05-12
申请人： Gregory G. Freeman , Anil K. Chinthakindi , David R. Greenberg , Basanth Jagannathan , Marwan H. Khater , John Pekarik , Xudong Wang
发明人： Gregory G. Freeman , Anil K. Chinthakindi , David R. Greenberg , Basanth Jagannathan , Marwan H. Khater , John Pekarik , Xudong Wang
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/665 , H01L29/66545 , H01L29/66659 , H01L29/7835 , H01L29/7843
摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.
摘要翻译：提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。栅极导体覆盖沟道区域。场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构，其中所述第二幅度具有从零到所述第一幅度的大约一半的值。在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

9. 发明授权

US06815802B2 Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology 有权
标题翻译：在硅/硅锗外延层中引入碳以提高Si-Ge双极技术的产量
公开(公告)号：US06815802B2
公开(公告)日：2004-11-09
申请号：US10122857
申请日：2002-04-15
申请人： Jack Oon Chu , Douglass Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
发明人： Jack Oon Chu , Douglass Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/02447 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/1004 , H01L29/161 , H01L29/7378
摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

10. 发明授权

US06429500B1 Semiconductor pin diode for high frequency applications 失效
标题翻译：半导体二极管用于高频应用
公开(公告)号：US06429500B1
公开(公告)日：2002-08-06
申请号：US09670587
申请日：2000-09-29
申请人： David R. Greenberg , Kathryn T. Schonenberg , Seshadri Subbanna , Keith M. Walter
发明人： David R. Greenberg , Kathryn T. Schonenberg , Seshadri Subbanna , Keith M. Walter
IPC分类号： H01L31075
CPC分类号： H01L29/66098 , H01L29/868
摘要： A microwave PIN diode having an increased intrinsic region volume for storing a charge. A semiconductor substrate has an N+ subcollector/cathode layer which encloses a region of the substrate. An N-skin formed over the interior of enclosed region. An Si layer is formed over the subcollector/cathode and N-skin to a thickness which defines the thickness for the intrinsic region of the diode. Implants are formed in the Si layer to permit contact with the subcollector/cathode layer. An anode is formed on the top of the Si layer. The total volume of the intrinsic region is increased by the N-skin which is positioned below the surface of the subcollector/cathode. The PIN diode may be formed as a lateral PIN diode thereby increasing the intrinsic region volume even further.
摘要翻译：具有增加的用于存储电荷的本征区域体积的微波PIN二极管。半导体衬底具有封装衬底的区域的N +子集电极/阴极层。在封闭区域的内部形成的N皮。在子集电极/阴极和N皮层上形成Si层，其厚度限定了二极管本征区域的厚度。在Si层中形成植入物以允许与子集电极/阴极层接触。阳极形成在Si层的顶部。本征区域的总体积由位于子集电极/阴极表面下方的N面增加。 PIN二极管可以形成为侧向PIN二极管，从而进一步增加本征区域体积。

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