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1. 发明授权

US08008698B2 Semiconductor memory devices having vertical channel transistors and related methods 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及相关方法
公开(公告)号：US08008698B2
公开(公告)日：2011-08-30
申请号：US12198266
申请日：2008-08-26
申请人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
发明人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/10876 , H01L27/10882 , H01L27/10885
摘要： A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.
摘要翻译：半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。还讨论了相关方法。

2. 发明申请

US20090121268A1 Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及相关方法
公开(公告)号：US20090121268A1
公开(公告)日：2009-05-14
申请号：US12198266
申请日：2008-08-26
申请人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
发明人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/10876 , H01L27/10882 , H01L27/10885
摘要： A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.
摘要翻译：半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。还讨论了相关方法。

3. 发明申请

US20110266627A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110266627A1
公开(公告)日：2011-11-03
申请号：US13096311
申请日：2011-04-28
申请人： Seung-hun Lee , Byeong-chan Lee , Sung-kwan Kang , Keum-seok Park , Yu-gyun Shin , Sun-ghil Lee
发明人： Seung-hun Lee , Byeong-chan Lee , Sung-kwan Kang , Keum-seok Park , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L27/092 , H01L27/085
CPC分类号： H01L21/823481 , H01L21/823878
摘要： A semiconductor device includes a semiconductor substrate including a plurality of active areas defined by a device isolation layer, a gate line structure crossing the plurality of active areas, a buffer insulation layer on the semiconductor substrate, the buffer insulation layer contacting a portion of a side of the gate line structure, a contact etching stopper layer on the buffer insulation layer, and a contact plug passing through the buffer insulation layer and the contact etching stopper layer to be connected to the plurality of active areas.
摘要翻译：半导体器件包括半导体衬底，其包括由器件隔离层限定的多个有源区，与多个有源区交叉的栅极线结构，半导体衬底上的缓冲绝缘层，缓冲绝缘层接触一侧的一部分栅极线结构，缓冲绝缘层上的接触蚀刻停止层以及通过缓冲绝缘层和接触蚀刻阻挡层的接触插塞，以连接到多个有源区。

4. 外观设计

USD679308S1 Monitoring camera 有权
公开(公告)号：USD679308S1
公开(公告)日：2013-04-02
申请号：US29391234
申请日：2011-05-05
申请人： Won-myung Park , Seung-hun Lee
设计人： Won-myung Park , Seung-hun Lee

5. 发明授权

US5742547A Circuits for block redundancy repair of integrated circuit memory devices 失效
标题翻译：集成电路存储器件的块冗余修复电路
公开(公告)号：US5742547A
公开(公告)日：1998-04-21
申请号：US701634
申请日：1996-08-22
申请人： Seung-hun Lee
发明人： Seung-hun Lee
IPC分类号： G11C11/401 , G06T1/60 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/81 , G06T1/60
摘要： A memory cell array includes a plurality of memory blocks, each of which includes normal memory cells and spare memory cells, arranged in arrays having rows and columns. A row or column of spare memory cells in one of the memory cell blocks is substituted for a defective row or column of normal memory cells in the one of the memory blocks, without substituting a row or column of spare memory cells in remaining ones of the memory cell blocks for a row or column of normal memory cells in the remaining ones of the memory blocks. Stated differently, a predetermined row or column of spare memory cells in a first one of the memory blocks is substituted for a first defective row or column of normal memory cells in the first one of the memory blocks, and the predetermined row or column of spare memory cells in a second one of the memory blocks is also substituted for a second defective row or column of normal memory cells in a second one of the memory blocks. Thus, a given row or column of spare memory cells can be used to substitute for different rows or columns of memory cells in each memory block. The number of spare memory cells which is required is thereby reduced.
摘要翻译：存储单元阵列包括多个存储块，每个存储块包括普通存储器单元和备用存储器单元，排列成具有行和列的阵列。其中一个存储单元块中的备用存储器单元的一行或一列代替存储器块中的一个存储器块中的一个有缺陷的行或列的常规存储器单元，而不用代替剩余存储器单元中的剩余存储器单元的行或列存储单元块，用于存储块中剩余存储单元中的正常存储器单元的行或列。换句话说，第一个存储块中的预定行或列备用存储器单元被替换为第一个存储块中的第一个缺陷行或一列常规存储器单元，并且预定的行或列的备用第二个存储块中的存储单元也被替换为第二个存储块中的第二个缺陷行或一列常规存储单元。因此，给定的行或列的备用存储单元可以用于替代每个存储块中的不同行或列的存储单元。从而减少了所需的备用存储单元的数量。

6. 发明授权

US5701271A Integrated circuit memory devices including banks of memory blocks 失效
标题翻译：集成电路存储器件包括存储器块组
公开(公告)号：US5701271A
公开(公告)日：1997-12-23
申请号：US703203
申请日：1996-08-26
申请人： Seung-hun Lee
发明人： Seung-hun Lee
IPC分类号： G11C11/41 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/409 , G11C13/00
CPC分类号： G11C7/10
摘要： An integrated circuit memory device includes a plurality of memory banks. Each of the memory banks includes a first array of at least four memory blocks and a second array of at least four memory blocks wherein each of the memory blocks includes at least two bit lines. Each of the memory blocks from the second array is paired with a respective memory block from the first array and the memory blocks are activated as pairs with at least one pair being activated during a data access operation. Four data lines are provided adjacent the first and second arrays of memory blocks. A plurality of input/output lines directly connects two of the bit lines from each of the memory blocks with two of the input/output lines so that for any pair of the memory blocks, two bit lines from each memory block of the pair are connected to separate data lines.
摘要翻译：集成电路存储器件包括多个存储体。每个存储体包括至少四个存储器块的第一阵列和至少四个存储器块的第二阵列，其中每个存储器块包括至少两个位线。来自第二阵列的每个存储器块与来自第一阵列的相应存储器块配对，并且存储块被激活成对，在数据访问操作期间至少有一对被激活。在第一和第二存储块阵列附近提供四条数据线。多个输入/输出线直接连接来自每个存储器块的两个位线与两个输入/输出线，使得对于任何一对存储器块，来自该对的每个存储器块的两个位线被连接分隔数据线。

7. 发明授权

US06298001B1 Semiconductor memory device enabling direct current voltage test in package status 失效
标题翻译：半导体存储器件，可实现封装状态下的直流电压测试
公开(公告)号：US06298001B1
公开(公告)日：2001-10-02
申请号：US08636428
申请日：1996-04-23
申请人： Seung-hun Lee , Tae-jin Kim
发明人： Seung-hun Lee , Tae-jin Kim
IPC分类号： G11C1700
CPC分类号： G11C29/48 , G11C29/50 , G11C2029/5004 , Y10T307/615
摘要： A semiconductor memory device for a package-state voltage test has a plurality of bonding pads that are electrically connected to an external device in a package state, at least one internal DC voltage generator, at least one switch connected between one of the bonding pads and the internal DC voltage generator. The switch is on during a test mode and is off during a normal mode. The switch controller is connected between at least two of the plurality of bonding pads and serves to control the switch in response to an external switching signal in the test mode. Because of this design, a number of DC voltage tests can be performed without increasing chip size since a general control pad also serves as a DC voltage test pad.
摘要翻译：一种用于封装状态电压测试的半导体存储器件，具有与封装状态的外部器件电连接的多个接合焊盘，至少一个内部直流电压发生器，至少一个开关，其连接在一个焊盘和内部直流电压发生器。开关在测试模式下打开，并在正常模式下关闭。开关控制器连接在多个接合焊盘中的至少两个接合焊盘之间，用于响应于测试模式中的外部开关信号来控制开关。由于这种设计，可以在不增加芯片尺寸的情况下执行多个直流电压测试，因为通用控制板也用作直流电压测试板。

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