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1. 发明授权

US08008698B2 Semiconductor memory devices having vertical channel transistors and related methods 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及相关方法
公开(公告)号：US08008698B2
公开(公告)日：2011-08-30
申请号：US12198266
申请日：2008-08-26
申请人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
发明人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/10876 , H01L27/10882 , H01L27/10885
摘要： A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.
摘要翻译：半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。还讨论了相关方法。

2. 发明申请

US20090121268A1 Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及相关方法
公开(公告)号：US20090121268A1
公开(公告)日：2009-05-14
申请号：US12198266
申请日：2008-08-26
申请人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
发明人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/10876 , H01L27/10882 , H01L27/10885
摘要： A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.
摘要翻译：半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。还讨论了相关方法。

3. 发明申请

US20110266627A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110266627A1
公开(公告)日：2011-11-03
申请号：US13096311
申请日：2011-04-28
申请人： Seung-hun Lee , Byeong-chan Lee , Sung-kwan Kang , Keum-seok Park , Yu-gyun Shin , Sun-ghil Lee
发明人： Seung-hun Lee , Byeong-chan Lee , Sung-kwan Kang , Keum-seok Park , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L27/092 , H01L27/085
CPC分类号： H01L21/823481 , H01L21/823878
摘要： A semiconductor device includes a semiconductor substrate including a plurality of active areas defined by a device isolation layer, a gate line structure crossing the plurality of active areas, a buffer insulation layer on the semiconductor substrate, the buffer insulation layer contacting a portion of a side of the gate line structure, a contact etching stopper layer on the buffer insulation layer, and a contact plug passing through the buffer insulation layer and the contact etching stopper layer to be connected to the plurality of active areas.
摘要翻译：半导体器件包括半导体衬底，其包括由器件隔离层限定的多个有源区，与多个有源区交叉的栅极线结构，半导体衬底上的缓冲绝缘层，缓冲绝缘层接触一侧的一部分栅极线结构，缓冲绝缘层上的接触蚀刻停止层以及通过缓冲绝缘层和接触蚀刻阻挡层的接触插塞，以连接到多个有源区。

4. 发明申请

US20110049596A1 Semiconductor Device Having Impurity Doped Polycrystalline Layer Including Impurity Diffusion Prevention Layer and Dynamic Random Memory Device Including the Semiconductor Device 有权
标题翻译：具有包括杂质扩散防止层的杂质掺杂多晶层的半导体器件和包括半导体器件的动态随机存储器件
公开(公告)号：US20110049596A1
公开(公告)日：2011-03-03
申请号：US12728396
申请日：2010-03-22
申请人： Dong-kak Lee , Sung-gil Kim , Soo-jin Hong , Sun-ghil Lee , Deok-hyung Lee
发明人： Dong-kak Lee , Sung-gil Kim , Soo-jin Hong , Sun-ghil Lee , Deok-hyung Lee
IPC分类号： H01L27/108 , H01L23/48 , H01L29/78
CPC分类号： H01L21/76843 , H01L21/28525 , H01L21/76847 , H01L21/76877 , H01L23/485 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.
摘要翻译：提供了包括半导体衬底，包括暴露半导体衬底的接触孔的绝缘层和填充接触孔的多晶硅层的半导体器件。多晶硅层掺杂有杂质，并且包括杂质扩散防止层。在半导体器件中，包含在多晶硅层中的杂质不会由于杂质扩散层而扩散到绝缘层和半导体衬底中。

5. 发明授权

US08692372B2 Semiconductor device having impurity doped polycrystalline layer including impurity diffusion prevention layer and dynamic random memory device including the semiconductor device 有权
标题翻译：具有包括杂质扩散防止层的杂质掺杂多晶层的半导体器件和包括该半导体器件的动态随机存储器件
公开(公告)号：US08692372B2
公开(公告)日：2014-04-08
申请号：US12728396
申请日：2010-03-22
申请人： Dong-kak Lee , Sung-gil Kim , Soo-jin Hong , Sun-ghil Lee , Deok-hyung Lee
发明人： Dong-kak Lee , Sung-gil Kim , Soo-jin Hong , Sun-ghil Lee , Deok-hyung Lee
IPC分类号： H01L27/108 , H01L23/48 , H01L29/78
CPC分类号： H01L21/76843 , H01L21/28525 , H01L21/76847 , H01L21/76877 , H01L23/485 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.
摘要翻译：提供了包括半导体衬底，包括暴露半导体衬底的接触孔的绝缘层和填充接触孔的多晶硅层的半导体器件。多晶硅层掺杂有杂质，并且包括杂质扩散防止层。在半导体器件中，包含在多晶硅层中的杂质不会由于杂质扩散层而扩散到绝缘层和半导体衬底中。

6. 发明授权

US07871897B2 Method of forming shallow trench isolation regions in devices with NMOS and PMOS regions 失效
标题翻译：在具有NMOS和PMOS区域的器件中形成浅沟槽隔离区的方法
公开(公告)号：US07871897B2
公开(公告)日：2011-01-18
申请号：US12466178
申请日：2009-05-14
申请人： Dong-woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
发明人： Dong-woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/10894 , H01L27/11546
摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
摘要翻译：在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。在单元区域，PMOS区域和NMOS区域中形成沟槽。在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。在衬底上形成第一器件隔离绝缘层，填充沟槽。去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

7. 发明申请

US20090311846A1 METHOD OF FORMING SHALLOW TRENCH ISOLATION REGIONS IN DEVICES WITH NMOS AND PMOS REGIONS 失效
标题翻译：在具有NMOS和PMOS区域的器件中形成低温分离区的方法
公开(公告)号：US20090311846A1
公开(公告)日：2009-12-17
申请号：US12466178
申请日：2009-05-14
申请人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
发明人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/10894 , H01L27/11546
摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
摘要翻译：在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。在单元区域，PMOS区域和NMOS区域中形成沟槽。在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。在衬底上形成第一器件隔离绝缘层，填充沟槽。去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

8. 发明授权

US08409947B2 Method of manufacturing semiconductor device having stress creating layer 有权
标题翻译：具有应力产生层的半导体器件的制造方法
公开(公告)号：US08409947B2
公开(公告)日：2013-04-02
申请号：US12693080
申请日：2010-01-25
申请人： Jin-bum Kim , Wook-je Kim , Yu-gyun Shin , Kwan-heum Lee , Sun-ghil Lee
发明人： Jin-bum Kim , Wook-je Kim , Yu-gyun Shin , Kwan-heum Lee , Sun-ghil Lee
IPC分类号： H01L21/8238
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.
摘要翻译：提供了一种制造具有应力产生层的半导体器件的简化方法。在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区第二区。第一和第二间隔物分别形成在第一和第二栅极的侧壁上。第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。去除第二半导体层。第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

9. 发明授权

US08361860B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08361860B2
公开(公告)日：2013-01-29
申请号：US12656130
申请日：2010-01-19
申请人： Jin-bum Kim , Wook-je Kim , Kwan-heum Lee , Yu-gyun Shin , Sun-ghil Lee
发明人： Jin-bum Kim , Wook-je Kim , Kwan-heum Lee , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L21/8242
CPC分类号： H01L21/7687 , H01L27/10855 , H01L28/91
摘要： A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.
摘要翻译：制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层，通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层的所述至少一个埋入式接触插塞。

10. 发明授权

US07956464B2 Sputtering target and semiconductor device manufactured using the same 失效
标题翻译：溅射靶和使用其制造的半导体器件
公开(公告)号：US07956464B2
公开(公告)日：2011-06-07
申请号：US12573437
申请日：2009-10-05
申请人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
发明人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L23/532
CPC分类号： H01L23/53266 , C23C14/185 , C23C14/3414 , H01L21/28088 , H01L2924/0002 , H01L2924/00
摘要： A sputtering target includes a tungsten (W)-nickel (Ni) alloy, wherein the nickel (Ni) is present in an amount of between about 0.01 weight % and about 1 weight %.
摘要翻译：溅射靶包括钨（W） - 镍（Ni）合金，其中镍（Ni）的存在量为约0.01重量％至约1重量％。

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