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1. 发明授权

US08450941B2 Systems and methods for dynamic power management for use with a video display device 失效
标题翻译：用于视频显示设备的动态电源管理的系统和方法
公开(公告)号：US08450941B2
公开(公告)日：2013-05-28
申请号：US13013700
申请日：2011-01-25
申请人： Dimitrios Katsis , Barry Concklin , Daryl Chamberlin , Peter J. Mole
发明人： Dimitrios Katsis , Barry Concklin , Daryl Chamberlin , Peter J. Mole
IPC分类号： H05B37/02
CPC分类号： G09G3/025 , G09G5/10 , G09G2320/043 , G09G2330/021 , G09G2360/145
摘要： Embodiments of the present invention relate to methods and circuits for use with a system including a light emitting element (e.g., a laser diode or light emitting diode) that is driven by a current produced by a current output digital-to-analog converter (DAC), wherein the light emitting element or the DAC is powered by a supply voltage produced by a voltage supply. In accordance with an embodiment, a measure indicative of a voltage at an output of the DAC is obtained, wherein the voltage at the output of the DAC is indicative of a voltage headroom available for the DAC. The measure indicative of the voltage at the output of the DAC is compared to one or more predetermined references, and the supply voltage is controlled based on the comparison(s).
摘要翻译：本发明的实施例涉及用于包括由电流输出数模转换器（DAC）产生的电流驱动的发光元件（例如，激光二极管或发光二极管）的系统的方法和电路），其中发光元件或DAC由电压源产生的电源电压供电。根据实施例，获得指示DAC输出处的电压的量度，其中DAC的输出处的电压表示可用于DAC的电压余量。将表示DAC输出端的电压的量度与一个或多个预定参考值相比较，并且基于比较来控制电源电压。

2. 发明申请

US20120153861A1 SYSTEMS AND METHODS FOR DYNAMIC POWER MANAGEMENT FOR USE WITH A VIDEO DISPLAY DEVICE 失效
标题翻译：用于动态显示设备的动态电源管理的系统和方法
公开(公告)号：US20120153861A1
公开(公告)日：2012-06-21
申请号：US13013700
申请日：2011-01-25
申请人： Dimitrios Katsis , Barry Concklin , Daryl Chamberlin , Peter J. Mole
发明人： Dimitrios Katsis , Barry Concklin , Daryl Chamberlin , Peter J. Mole
IPC分类号： H05B37/02
CPC分类号： G09G3/025 , G09G5/10 , G09G2320/043 , G09G2330/021 , G09G2360/145
摘要： Embodiments of the present invention relate to methods and circuits for use with a system including a light emitting element (e.g., a laser diode or light emitting diode) that is driven by a current produced by a current output digital-to-analog converter (DAC), wherein the light emitting element or the DAC is powered by a supply voltage produced by a voltage supply. In accordance with an embodiment, a measure indicative of a voltage at an output of the DAC is obtained, wherein the voltage at the output of the DAC is indicative of a voltage headroom available for the DAC. The measure indicative of the voltage at the output of the DAC is compared to one or more predetermined references, and the supply voltage is controlled based on the comparison(s).
摘要翻译：本发明的实施例涉及用于包括由电流输出数模转换器（DAC）产生的电流驱动的发光元件（例如，激光二极管或发光二极管）的系统的方法和电路），其中发光元件或DAC由电压源产生的电源电压供电。根据实施例，获得指示DAC输出处的电压的量度，其中DAC的输出处的电压表示可用于DAC的电压余量。将表示DAC输出端的电压的量度与一个或多个预定参考值相比较，并且基于比较来控制电源电压。

3. 发明申请

US20090243720A1 AMPLIFIERS WITH NEGATIVE CAPACITANCE CIRCUITS 有权
标题翻译：具有负电容电路的放大器
公开(公告)号：US20090243720A1
公开(公告)日：2009-10-01
申请号：US12475409
申请日：2009-05-29
申请人： Philip V. Golden , Peter J. Mole
发明人： Philip V. Golden , Peter J. Mole
IPC分类号： H03F1/26
CPC分类号： H03H11/481
摘要： Provided herein are amplifiers including negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of output stages of such amplifiers. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion. Also provided herein are methods for use with amplifiers including an output stage, including connecting a negative capacitance circuit in parallel with a base-emitter capacitance of the output stage.
摘要翻译：这里提供的放大器包括负电容电路，用于减少由这种放大器的输出级的栅源（或基极 - 发射极）电容引起的失真。这种负电容电路与输出级的栅源（或基极 - 发射极）电容并联连接，以分流栅源（或基极 - 发射极）电容，从而减少失真。本文还提供了与包括输出级的放大器一起使用的方法，包括将负电容电路与输出级的基极 - 发射极电容并联连接。

4. 发明授权

US07863980B2 Amplifiers with negative capacitance circuits 有权
标题翻译：具有负电容电路的放大器
公开(公告)号：US07863980B2
公开(公告)日：2011-01-04
申请号：US12475409
申请日：2009-05-29
申请人： Philip V. Golden , Peter J. Mole
发明人： Philip V. Golden , Peter J. Mole
IPC分类号： H03F1/26
CPC分类号： H03H11/481
摘要： Provided herein are amplifiers including negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of output stages of such amplifiers. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion. Also provided herein are methods for use with amplifiers including an output stage, including connecting a negative capacitance circuit in parallel with a base-emitter capacitance of the output stage.
摘要翻译：这里提供的放大器包括负电容电路，用于减少由这种放大器的输出级的栅源（或基极 - 发射极）电容引起的失真。这种负电容电路与输出级的栅源（或基极 - 发射极）电容并联连接，以分流栅源（或基极 - 发射极）电容，从而减少失真。本文还提供了与包括输出级的放大器一起使用的方法，包括将负电容电路与输出级的基极 - 发射极电容并联连接。

5. 发明申请

US20080129424A1 NEGATIVE CAPACITANCE SYNTHESIS 有权
标题翻译：负电容合成
公开(公告)号：US20080129424A1
公开(公告)日：2008-06-05
申请号：US11567114
申请日：2006-12-05
申请人： Philip V. Golden , Peter J. Mole
发明人： Philip V. Golden , Peter J. Mole
IPC分类号： H03H11/00
CPC分类号： H03H11/481
摘要： Provided herein are negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of an output stage. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance ofthe output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion.
摘要翻译：这里提供了用于减少由输出级的栅源（或基极 - 发射极）电容产生的失真的负电容电路。这种负电容电路与输出级的栅源（或基极 - 发射极）电容并联连接，以分流栅源（或基极 - 发射极）电容，从而减少失真。

6. 发明授权

US07053698B2 Methods for extracting the mean (common mode) voltage of two input signals 失效
标题翻译：提取两个输入信号的平均（共模）电压的方法
公开(公告)号：US07053698B2
公开(公告)日：2006-05-30
申请号：US11041661
申请日：2005-01-24
申请人： Peter J. Mole
发明人： Peter J. Mole
IPC分类号： G06G7/12
CPC分类号： H03F3/45098 , H03F2203/45418 , H03F2203/45521 , H03F2203/45652
摘要： Methods and circuits for extracting a true mean of two signals are provided. A first amplifier input stage (e.g., an n-type stage) is operated when a mean of the two signals approaches an upper rail voltage. A second amplifier input stage (e.g., a p-type stage) is operated when the mean of the two signals approaches a lower rail voltage. A transitioning circuit controls how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage, when the mean of the two signal does not approach either of the rail voltages. An output of the high-gain amplifier output stage is fed back to both the first and second amplifier input stages via a feedback stage, which can be a matched buffer stage.
摘要翻译：提供了用于提取两个信号的真实均值的方法和电路。当两个信号的平均值接近上轨道电压时，第一放大器输入级（例如，n型级）被操作。当两个信号的平均值接近较低的轨道电压时，第二放大器输入级（例如，p型级）被操作。当两个信号的平均值不接近任一轨道电压时，转换电路控制第一和第二放大器输入级中的每一个对多个高增益放大器输出级的输入贡献多少。高增益放大器输出级的输出通过反馈级反馈到第一和第二放大器输入级，反馈级可以是匹配的缓冲级。

7. 发明授权

US08908092B2 Systems and methods to improve spatial resolution on back and forth scanning display devices 有权
标题翻译：提高前后扫描显示装置的空间分辨率的系统和方法
公开(公告)号：US08908092B2
公开(公告)日：2014-12-09
申请号：US13536556
申请日：2012-06-28
申请人： Morgan Tang , Peter J. Mole , Jayant Vivrekar
发明人： Morgan Tang , Peter J. Mole , Jayant Vivrekar
IPC分类号： H04N7/01
CPC分类号： H04N9/3135 , H04N9/3188
摘要： Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).
摘要翻译：本文所述的方法，系统和装置提高了由扫描投影仪显示装置产生的四角形图像的侧面的垂直分辨率。根据一个实施例，图像的第一多个帧（例如，奇数帧）在一个角部中从第一行开始从一侧到另一侧进行扫描。此外，图像的第二组多个帧（例如，偶数帧）在相同的一个角中从第一行级的垂直偏移水平开始从一侧到另一侧进行扫描。对第一多个帧（例如，奇数帧）的扫描与第二多个帧（例如，偶数帧）的扫描进行交织。

8. 发明授权

US08228120B2 Negative capacitance synthesis for use with differential circuits 失效
标题翻译：用于差分电路的负电容合成
公开(公告)号：US08228120B2
公开(公告)日：2012-07-24
申请号：US12604955
申请日：2009-10-23
申请人： Peter J. Mole , Philip V. Golden
发明人： Peter J. Mole , Philip V. Golden
IPC分类号： H03F3/45
CPC分类号： H03F3/4508 , H03F3/45098 , H03F3/45179 , H03F3/45493 , H03F2203/45394 , H03F2203/45458 , H03F2203/45631 , H03F2203/45652 , H03H11/481
摘要： Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.
摘要翻译：这里提供了减小差分电路的差分节点处的差分电容同时提高差分节点处的共模电容的方法和电路，其中差分电路包括一对输入和差分输出。在差分电路的差分节点之间产生负电容，这可以通过在差分电路的差分节点之间连接负电容电路来实现。在一个实施例中，负电容电路与差分电路的差分输出并联连接。在另一个实施例中，负电容电路与差分电路的输入并联连接。在另一个实施例中，负电容电路与差分电路的差分内部节点（即，除了输入和输出节点之外的节点）并联连接。

9. 发明申请

US20130235266A1 SYSTEMS AND METHODS TO IMPROVE SPATIAL RESOLUTION ON BACK AND FORTH SCANNING DISPLAY DEVICES 有权
标题翻译：用于改进背景和扫描显示装置上的空间分辨率的系统和方法
公开(公告)号：US20130235266A1
公开(公告)日：2013-09-12
申请号：US13536556
申请日：2012-06-28
申请人： Morgan Tang , Peter J. Mole , Jayant Vivrekar
发明人： Morgan Tang , Peter J. Mole , Jayant Vivrekar
IPC分类号： H04N7/01
CPC分类号： H04N9/3135 , H04N9/3188
摘要： Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).
摘要翻译：本文所述的方法，系统和装置提高了由扫描投影仪显示装置产生的四角形图像的侧面的垂直分辨率。根据一个实施例，图像的第一多个帧（例如，奇数帧）在一个角部中从第一行开始从一侧到另一侧进行扫描。此外，图像的第二组多个帧（例如，偶数帧）在相同的一个角中从第一行级的垂直偏移水平开始从一侧到另一侧进行扫描。对第一多个帧（例如，奇数帧）的扫描与第二多个帧（例如，偶数帧）的扫描进行交织。

10. 发明授权

US08339198B2 Negative capacitance synthesis for use with differential circuits 失效
公开(公告)号：US08339198B2
公开(公告)日：2012-12-25
申请号：US13534622
申请日：2012-06-27
申请人： Peter J. Mole , Philip V. Golden
发明人： Peter J. Mole , Philip V. Golden
IPC分类号： H03F3/45
CPC分类号： H03F3/4508 , H03F3/45098 , H03F3/45179 , H03F3/45493 , H03F2203/45394 , H03F2203/45458 , H03F2203/45631 , H03F2203/45652 , H03H11/481
摘要： Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.

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