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    • 4. 发明授权
    • Method and apparatus for decoding paging message in wireless communication system
    • 在无线通信系统中解码寻呼消息的方法和装置
    • US08219118B2
    • 2012-07-10
    • US11566753
    • 2006-12-05
    • Hee-Su KimDong-Wook SeoIl-Yong Jong
    • Hee-Su KimDong-Wook SeoIl-Yong Jong
    • H04W68/00
    • H04W68/00H04W52/0229Y02D70/1222Y02D70/1224
    • A method and mobile device for decoding a paging message transmitted as multiple bursts in a wireless communication system are provided. In the method, only the first burst among four bursts of a transmitted paging message is received and equalized. The equalized first burst is compared (e.g., by computing correlation) with a reference paging message. The first comparison result value obtained from the first comparison is compared with a threshold value. If the first comparison result value is greater than the threshold value, second through fourth bursts of the paging message are not received, and a previous decoded paging message is output and a sleep state is entered. If the comparison result value is not greater than the threshold value, the second through fourth bursts are received and decoded, the decoded paging message is encoded, and a first burst of the encoded paging message is stored as the reference paging message.
    • 提供了一种用于解码在无线通信系统中作为多个突发发送的寻呼消息的方法和移动设备。 在该方法中,仅接收并均衡发送的寻呼消息的四个突发中的第一个突发。 将均衡的第一突发与参考寻呼消息进行比较(例如,通过计算相关性)。 将从第一比较获得的第一比较结果值与阈值进行比较。 如果第一比较结果值大于阈值,则不接收到寻呼消息的第二到第四突发,并且输出先前解码的寻呼消息并输入睡眠状态。 如果比较结果值不大于阈值,则接收和解码第二至第四突发,解码的寻呼消息被编码,并且编码的寻呼消息的第一突发被存储为参考寻呼消息。
    • 5. 发明申请
    • METHOD AND APPARATUS FOR DECODING PAGING MESSAGE IN WIRELESS COMMUNICATION SYSTEM
    • 用于在无线通信系统中解码寻呼消息的方法和装置
    • US20070184866A1
    • 2007-08-09
    • US11566753
    • 2006-12-05
    • Hee-Su KimDong-Wook SeoIl-Yong Jong
    • Hee-Su KimDong-Wook SeoIl-Yong Jong
    • H04B7/00
    • H04W68/00H04W52/0229Y02D70/1222Y02D70/1224
    • A method and mobile device for decoding a paging message transmitted as multiple bursts in a wireless communication system are provided. In the method, only the first burst among four bursts of a transmitted paging message is received and equalized. The equalized first burst is compared (e.g., by computing correlation) with a reference paging message. The first comparison result value obtained from the first comparison is compared with a threshold value. If the first comparison result value is greater than the threshold value, second through fourth bursts of the paging message are not received, and a previous decoded paging message is output and a sleep state is entered. If the comparison result value is not greater than the threshold value, the second through fourth bursts are received and decoded, the decoded paging message is encoded, and a first burst of the encoded paging message is stored as the reference paging message.
    • 提供了一种用于解码在无线通信系统中作为多个突发发送的寻呼消息的方法和移动设备。 在该方法中,仅接收并均衡发送的寻呼消息的四个突发中的第一个突发。 将均衡的第一突发与参考寻呼消息进行比较(例如,通过计算相关性)。 将从第一比较获得的第一比较结果值与阈值进行比较。 如果第一比较结果值大于阈值,则不接收到寻呼消息的第二到第四突发,并且输出先前解码的寻呼消息并输入睡眠状态。 如果比较结果值不大于阈值,则接收和解码第二至第四突发,解码的寻呼消息被编码,并且编码的寻呼消息的第一突发被存储为参考寻呼消息。
    • 7. 发明授权
    • Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations
    • 其中具有限幅电路的多端口存储器件在重写写入和读取操作期间阻止数据错误
    • US07894296B2
    • 2011-02-22
    • US12496976
    • 2009-07-02
    • Chan-Ho LeeDong-Wook Seo
    • Chan-Ho LeeDong-Wook Seo
    • G11C7/12
    • G11C8/16
    • An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.
    • 集成电路器件包括其中具有多端口存储器单元(例如,双端口SRAM单元)的存储器阵列。 该多端口存储单元至少包括第一和第二读/写端口,其可由响应于字线信号的相应存取晶体管(例如,N型MOS晶体管)提供。 第一和第二读/写端口分别电耦合到第一和第二位线。 还提供了第一限幅电路。 第一限幅电路响应于第一写入控制信号。 第一限幅电路被配置为在第一“重叠”操作期间以读取阻断电压偏置第一位线,以将来自第二位线的数据从多端口存储器单元读取数据同时写入多端口存储器单元 到第一个位线。
    • 8. 发明授权
    • Power gating circuit, system on chip circuit including the same and power gating method
    • 电源门控电路,片上电路包括相同的电源门控方式
    • US07782701B2
    • 2010-08-24
    • US11846677
    • 2007-08-29
    • Dong-Wook SeoJong-Hoon JungIn-Gyu ParkChan-Ho Lee
    • Dong-Wook SeoJong-Hoon JungIn-Gyu ParkChan-Ho Lee
    • G11C5/14
    • G11C5/14H03K19/0016
    • A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.
    • 存储器件的电源门控电路包括电源门控单元和控制单元。 电源门控单元包括并联连接在存储器件的电源电压和内部电源电压总线之间的第一,第二和第三电源门控晶体管。 三个电源门控晶体管依次导通。 第二和第三电源门控晶体管响应于总线的电压增加而依次接通。 当第二和第三功率选通晶体管依次导通时的定时点是基于检测到逐渐增加内部电源电压的电压电平。 第一功率门控晶体管的尺寸可以小于第二功率门控晶体管的尺寸,并且第二功率门控晶体管的尺寸可以小于第三功率门控晶体管的尺寸。
    • 9. 发明授权
    • Memory device and method for precharging a memory device
    • 用于对存储器件进行预充电的存储器件和方法
    • US07599237B2
    • 2009-10-06
    • US11843379
    • 2007-08-22
    • Jong-Hoon JungDong-Wook Seo
    • Jong-Hoon JungDong-Wook Seo
    • G11C8/00
    • G11C7/12G11C7/18G11C11/413G11C2207/005
    • A memory device having a short precharge time is included. The memory device selects at least two pairs of bit lines and connects the selected two pairs of bit lines to the sense amplifier within a preparatory period during which the two pairs of bit lines and an input to the sense amplifier are precharged. In the preparatory period an input unit of the sense amplifier is precharged through by a plurality of precharge units through more than two bit lines, and thus the precharge time may be decreased. The memory device selects one pair of bit lines and connects the selected pair of bit lines to a sense amplifier within a read/write (data transmission) period.
    • 包括具有较短预充电时间的存储器件。 存储器件选择至少两对位线,并且在所述两对位线和对读出放大器的输入进行预充电的预备时段内将所选择的两对位线连接到读出放大器。 在预备期间,读出放大器的输入单元通过多于两个位线的多个预充电单元进行预充电,从而可以减少预充电时间。 存储器件选择一对位线,并将所选择的位线对连接到读/写(数据传输)周期内的读出放大器。