专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09559875B2 Blind equalization in a single carrier wideband channel 有权
标题翻译：单载波宽带信道中的盲均衡
公开(公告)号：US09559875B2
公开(公告)日：2017-01-31
申请号：US13467394
申请日：2012-05-09
申请人： Daniel N. Liu , Michael P. Fitz
发明人： Daniel N. Liu , Michael P. Fitz
IPC分类号： H04L25/03
CPC分类号： H04L25/0305 , H04L25/03038 , H04L2025/03407 , H04L2025/0342 , H04L2025/03636
摘要： A blind equalizer apparatus includes a decision-directed (DD) least mean squares (LMS) blind equalizer. A blind equalizer apparatus includes: a DD LMS blind equalizer, wherein: the blind equalizer uses a finite impulse response filter with tap weights that are adaptively updated using a filter tap update algorithm, wherein blind equalization of one of an in-phase (I) channel and a quadrature (Q) channel is carried out by maximizing the Euclidean distance of binary modulated waveforms, wherein the blind equalizer averages a block to compute an independent phase estimate for a block, wherein the blind equalizer computes an error variable for a block from the phase estimate for the block, wherein the blind equalizer uses the phase estimate and alternating I/Q one dimensional/binary slicing to make a hard decision, and wherein the blind equalizer uses the hard decision to derive an error variable that is used to update the filter tap weights.
摘要翻译：盲均衡器装置包括决策导向（DD）最小均方（LMS）盲均衡器。盲均衡器装置包括：DD LMS盲均衡器，其中：盲均衡器使用具有抽头权重的有限脉冲响应滤波器，使用滤波器抽头更新算法自适应地更新，其中，同步（I）通过最大化二进制调制波形的欧几里得距离来执行正交（Q）信道，其中盲均衡器对块进行平均以计算块的独立相位估计，其中盲均衡器计算块的误差变量所述盲均衡器使用所述相位估计和交替I / Q一维/二进制切片作出硬判决，并且其中所述盲均衡器使用所述硬判决来导出用于更新的误差变量过滤器抽头重量。

2. 发明申请

US20130259112A1 VARIABLE-PRECISION DISTRIBUTED ARITHMETIC MULTI-INPUT MULTI-OUTPUT EQUALIZER FOR POWER-AND-AREA-EFFICIENT OPTICAL DUAL-POLARIZATION QUADRATURE PHASE-SHIFT-KEYING SYSTEM 有权
标题翻译：可变精度分布式算法多输入多输出均衡器，用于功率和区域有效的光学双极化平衡相位移键控系统
公开(公告)号：US20130259112A1
公开(公告)日：2013-10-03
申请号：US13740118
申请日：2013-01-11
申请人： Korea Advanced Institute of Science and Technology
发明人： Hyeon Min BAE , Soon Won KWON
IPC分类号： H04L25/03
CPC分类号： H04L25/03891 , H04L25/03961 , H04L2025/03407
摘要： A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer is presented to reduce the size and dynamic power of 112 Gbps dual-polarization quadrature phase-shift-keying (DP-QPSK) coherent optical communication receivers. The VPDA MIMO equalizer compensates for channel dispersion as well as various non-idealities of a time-interleaved successive approximation register (SAR) based analog-to-digital converter (ADC) simultaneously by using a least mean square (LMS) algorithm. As a result, area-hungry analog domain calibration circuits are not required. In addition, the VPDA MIMO equalizer achieves 45% dynamic power reduction over conventional finite impulse response (FIR) to equalizers by utilizing the minimum required resolution for the equalization of each dispersed symbol.
摘要翻译：提出了一种可变精度分布算法（VPDA）多输入多输出（MIMO）均衡器，以减小112 Gbps双极化正交相移键控（DP-QPSK）相干光通信接收机的大小和动态功耗。 VPDA MIMO均衡器通过使用最小均方（LMS）算法同时补偿时间交错逐次逼近寄存器（SAR）的模数转换器（ADC）的信道色散以及各种非理想性。因此，不需要占地面积的模拟域校准电路。此外，VPDA MIMO均衡器通过利用每个分散符号的均衡的最小所需分辨率，实现了对均衡器的传统有限脉冲响应（FIR）的45％的动态功率降低。

3. 发明授权

US08406350B2 Joint demodulation using a viterbi equalizer having an adaptive total number of states 有权
标题翻译：使用具有自适应总数状态的维特比均衡器的联合解调
公开(公告)号：US08406350B2
公开(公告)日：2013-03-26
申请号：US13286565
申请日：2011-11-01
申请人： Richard A. Kobylinski , David Randall Wolter
发明人： Richard A. Kobylinski , David Randall Wolter
IPC分类号： H04L27/06
CPC分类号： H04L25/0208 , H04B1/1081 , H04L25/0204 , H04L25/0212 , H04L25/0224 , H04L25/03 , H04L25/03178 , H04L25/03197 , H04L25/03203 , H04L25/03331 , H04L27/2017 , H04L2025/03407
摘要： Systems and methods for performing joint demodulation using a Viterbi equalizer having an adaptive total number of states are disclosed. Generally, a method includes joint demodulating a desired signal and one or more interfering signals with a Viterbi equalizer having an adaptive total number of states based on channel impulse response (CIR) coefficients associated with a desired signal and the one or more interfering signals.
摘要翻译：公开了使用具有自适应总数状态的维特比均衡器执行联合解调的系统和方法。通常，一种方法包括基于与期望信号和一个或多个干扰信号相关联的信道脉冲响应（CIR）系数，将具有自适应总数状态的维特比均衡器的所需信号和一个或多个干扰信号联合解调。

4. 发明授权

US07974370B2 Parallel processing for single antenna interference cancellation 有权
标题翻译：单天线干扰消除的并行处理
公开(公告)号：US07974370B2
公开(公告)日：2011-07-05
申请号：US11616410
申请日：2006-12-27
申请人： Brian T. Kelley
发明人： Brian T. Kelley
IPC分类号： H03D1/04 , H03D1/06 , H03K5/01 , H03K6/04 , H04B1/10 , H04L1/00 , H04L25/08 , H04B15/00
CPC分类号： H04L25/03038 , H04L2025/03407
摘要： A system and method is disclosed for providing single antenna interference cancellation processing with minimum latency. Incoming data frames are processed to generate a plurality of parallel data streams which are then further processed using a parallel single antenna interference cancellation algorithm to reject the signals and to generate a data stream containing only the desired symbols. In various embodiments of the invention, the parallel data streams are processed using a parallel arithmetic logic unit that is capable of operating in single-cycle mode in response to a first control stream and a multi-cycle mode in response to a second control stream. Embodiments of the invention comprise a three port memory interface operable to receive the parallel data streams and to generate a virtual three-dimensional data structure therefrom. In some embodiments of the invention, the virtual three-dimensional data representation comprises a plurality of segmented matrices, with the segmented matrices comprising data corresponding to portions of the incoming data frames. Data elements within the individual segments of the virtual three dimensional data structure can be calculated using data elements contained in a predetermined row and predetermined column of a segment.
摘要翻译：公开了一种用于以最小延迟提供单天线干扰消除处理的系统和方法。处理进入的数据帧以产生多个并行数据流，然后使用并行单天线干扰消除算法进一步处理以排除信号并产生仅包含期望符号的数据流。在本发明的各种实施例中，使用并行算术逻辑单元处理并行数据流，该并行算术逻辑单元响应于第一控制流和响应于第二控制流的多循环模式，能够以单周期模式运行。本发明的实施例包括可操作以接收并行数据流并从其生成虚拟三维数据结构的三端口存储器接口。在本发明的一些实施例中，虚拟三维数据表示包括多个分段矩阵，分割矩阵包括对应于输入数据帧的部分的数据。可以使用包含在段的预定行和预定列中的数据元素来计算虚拟三维数据结构的各个段内的数据元素。

5. 发明申请

US20090185635A1 Communication System, Transmitter, Receiver and Multiple Access Method 有权
标题翻译：通信系统，发射机，接收机和多址接入方式
公开(公告)号：US20090185635A1
公开(公告)日：2009-07-23
申请号：US12308849
申请日：2007-06-15
申请人： James Awuor Okello
发明人： James Awuor Okello
IPC分类号： H04B7/02 , H04L27/00
CPC分类号： H04B7/0613 , H04B1/7107 , H04B7/0837 , H04L25/0305 , H04L25/03343 , H04L25/03866 , H04L2025/03407 , H04L2025/03426
摘要： In a communications system including a transmitter for transmitting signals over a transmission channel and a receiver for receiving the signals, the transmitter includes: a filter for filtering a modulated signal to modify amplitude and phase characteristics of the modulated signal; and a first processor for performing interleaving process and/or scrambling process for the filtered signal. On the other hand, the receiver includes: a second processor for performing deinterleaving process and/or descrambling process for a received signal; and an inverse filter for filtering a signal supplied from the second processor.
摘要翻译：在包括用于通过传输信道发送信号的发射机和用于接收信号的接收机的通信系统中，发射机包括：滤波器，用于对调制信号进行滤波，以修改调制信号的幅度和相位特性; 以及用于对经滤波的信号执行交织处理和/或加扰处理的第一处理器。另一方面，接收机包括：用于对接收到的信号执行解交织处理和/或解扰处理的第二处理器; 以及用于对从第二处理器提供的信号进行滤波的逆滤波器。

6. 发明授权

US07545893B2 Single antenna interference cancellation via complement subspace projection in spatial-temporal expansion of noise estimation 有权
标题翻译：通过补充子空间投影在噪声估计的空间 - 时间扩展中的单天线干扰消除
公开(公告)号：US07545893B2
公开(公告)日：2009-06-09
申请号：US11287445
申请日：2005-11-28
申请人： Shousheng He
发明人： Shousheng He
IPC分类号： H03D1/04
CPC分类号： H04B1/1027 , H04L25/03006 , H04L25/03993 , H04L2025/03407
摘要： Interference rejection in a wireless communication system involves determining a complement spatial-temporal signal subspace that is complement to a spatial-temporal signal subspace of an interference signal included in a received signal. The received signal is projected onto the complement spatial-temporal signal subspace, whereby the interference signal included in the received signal is reduced. Determining the complement spatial-temporal signal subspace can include estimating the interference signal; determining a Block Yule-Walker matrix for the estimated interference signal; and determining the complement spatial-temporal signal subspace from the Block Yule-Walker matrix.
摘要翻译：无线通信系统中的干扰抑制涉及确定与接收信号中包含的干扰信号的空间 - 时间信号子空间互补的补码空间 - 时间信号子空间。接收的信号被投影到补码空间 - 时间信号子空间上，从而减少包含在接收信号中的干扰信号。确定补码空间 - 时间信号子空间可以包括估计干扰信号; 确定所估计的干扰信号的块Yule-Walker矩阵; 以及从块Yule-Walker矩阵确定补码空间 - 时间信号子空间。

7. 发明申请

US20080159452A1 Parallel processing for single antenna interference cancellation 有权
标题翻译：单天线干扰消除的并行处理
公开(公告)号：US20080159452A1
公开(公告)日：2008-07-03
申请号：US11616410
申请日：2006-12-27
申请人： Brian T. Kelley
发明人： Brian T. Kelley
IPC分类号： H04B1/10
CPC分类号： H04L25/03038 , H04L2025/03407
摘要： A system and method is disclosed for providing single antenna interference cancellation processing with minimum latency. Incoming data frames are processed to generate a plurality of parallel data streams which are then further processed using a parallel single antenna interference cancellation algorithm to reject the signals and to generate a data stream containing only the desired symbols. In various embodiments of the invention, the parallel data streams are processed using a parallel arithmetic logic unit that is capable of operating in single-cycle mode in response to a first control stream and a multi-cycle mode in response to a second control stream. Embodiments of the invention comprise a three port memory interface operable to receive the parallel data streams and to generate a virtual three-dimensional data structure therefrom. In some embodiments of the invention, the virtual three-dimensional data representation comprises a plurality of segmented matrices, with the segmented matrices comprising data corresponding to portions of the incoming data frames. Data elements within the individual segments of the virtual three dimensional data structure can be calculated using data elements contained in a predetermined row and predetermined column of a segment.
摘要翻译：公开了一种用于以最小延迟提供单天线干扰消除处理的系统和方法。处理进入的数据帧以产生多个并行数据流，然后使用并行单天线干扰消除算法进一步处理以排除信号并产生仅包含期望符号的数据流。在本发明的各种实施例中，使用并行算术逻辑单元处理并行数据流，该并行算术逻辑单元响应于第一控制流和响应于第二控制流的多循环模式，能够以单周期模式运行。本发明的实施例包括可操作以接收并行数据流并从其生成虚拟三维数据结构的三端口存储器接口。在本发明的一些实施例中，虚拟三维数据表示包括多个分段矩阵，分割矩阵包括对应于输入数据帧的部分的数据。可以使用包含在段的预定行和预定列中的数据元素来计算虚拟三维数据结构的各个段内的数据元素。

8. 发明授权

US07366254B2 Edge incremental redundancy support in a cellular wireless terminal 失效
标题翻译：蜂窝无线终端中的边缘增量冗余支持
公开(公告)号：US07366254B2
公开(公告)日：2008-04-29
申请号：US11636032
申请日：2006-12-08
申请人： Li Fung Chang , Nelson R. Sollenberger , Yongqian Wang , Aki Shohara , Yue Chen
发明人： Li Fung Chang , Nelson R. Sollenberger , Yongqian Wang , Aki Shohara , Yue Chen
IPC分类号： H03K9/00
CPC分类号： H04L1/0059 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L1/0065 , H04L1/0068 , H04L1/0069 , H04L1/0071 , H04L1/1816 , H04L1/1819 , H04L1/1829 , H04L1/1835 , H04L1/1845 , H04L1/203 , H04L1/208 , H04L25/03006 , H04L25/03318 , H04L25/067 , H04L27/0008 , H04L2025/03401 , H04L2025/03407 , H04L2025/03726 , H04L2027/0038
摘要： A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, and an IR processing module. The baseband processor receives an analog signal corresponding to a data block and samples the analog signal to produce samples. The equalizer receives the samples from the baseband processor, equalizes the samples, and produces soft decision bits corresponding to the data block. The equalizer may be implemented as a distinct processing component or may be performed by the baseband processor or system processor. The system processor receives at least the soft decision bits and initiates IR operations. The IR processing module receives the soft decision bits of the data block and performs IR operations on the data block in an attempt to correctly decode a corresponding data block.
摘要翻译：用于在无线接收机中实现增量冗余（IR）操作的系统包括基带处理器，均衡器，系统处理器和IR处理模块。基带处理器接收对应于数据块的模拟信号，并对模拟信号进行采样以产生采样。均衡器从基带处理器接收样本，对采样进行均衡，并产生与数据块相对应的软判决位。均衡器可以被实现为不同的处理组件，或者可以由基带处理器或系统处理器执行。系统处理器至少接收软判决位，并启动IR操作。 IR处理模块接收数据块的软判决位，并对数据块执行IR操作，以试图正确解码对应的数据块。

9. 发明申请

US20070288547A1 EDGE INCREMENTAL REDUNDANCY MEMORY STRUCTURE AND MEMORY MANAGEMENT 有权
标题翻译：边缘增长冗余存储结构和内存管理
公开(公告)号：US20070288547A1
公开(公告)日：2007-12-13
申请号：US11843903
申请日：2007-08-23
申请人： Li Fung Chang , Yongqian Wang
发明人： Li Fung Chang , Yongqian Wang
IPC分类号： G06F15/16
CPC分类号： H04L1/0059 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L1/0065 , H04L1/0068 , H04L1/0069 , H04L1/0071 , H04L1/1816 , H04L1/1819 , H04L1/1829 , H04L1/1835 , H04L1/1845 , H04L1/203 , H04L1/208 , H04L25/03006 , H04L25/03318 , H04L25/067 , H04L27/0008 , H04L2025/03401 , H04L2025/03407 , H04L2025/03726 , H04L2027/0038
摘要： A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes at least one processing device, an IR processing function, and IR memory. The at least one processing device is operable to receive analog signals corresponding to a data block, to sample the analog signals to produce samples, to equalize the samples to produce soft decision bits corresponding to the data block, and to initiate IR operations. The IR processing function is operable to perform IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block. The IR memory operably couples to the IR processing function, includes Type I IR memory adapted to store IR status information of the data block, and includes Type II IR memory adapted to store the data block.
摘要翻译：用于在无线接收机中实现增量冗余（IR）操作的系统包括至少一个处理设备，IR处理功能和IR存储器。所述至少一个处理装置可操作以接收对应于数据块的模拟信号，以对所述模拟信号进行采样以产生样本，以使样本均衡以产生与所述数据块相对应的软判决位，并发起IR操作。 IR处理功能可操作以对数据块的软判决位执行IR操作，以尝试正确解码数据块。 IR存储器可操作地耦合到IR处理功能，包括适于存储数据块的IR状态信息的I型IR存储器，并且包括适于存储数据块的II型IR存储器。

10. 发明授权

US07272768B2 Edge incremental redundancy memory structure and memory management 有权
标题翻译：边增量冗余内存结构和内存管理
公开(公告)号：US07272768B2
公开(公告)日：2007-09-18
申请号：US10731804
申请日：2003-12-09
申请人： Li Fung Chang , Yongqian Wang
发明人： Li Fung Chang , Yongqian Wang
IPC分类号： H03M13/00
CPC分类号： H04L1/0059 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L1/0065 , H04L1/0068 , H04L1/0069 , H04L1/0071 , H04L1/1816 , H04L1/1819 , H04L1/1829 , H04L1/1835 , H04L1/1845 , H04L1/203 , H04L1/208 , H04L25/03006 , H04L25/03318 , H04L25/067 , H04L27/0008 , H04L2025/03401 , H04L2025/03407 , H04L2025/03726 , H04L2027/0038
摘要： A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes at least one processing device, an IR processing function, and IR memory. The at least one processing device is operable to receive analog signals corresponding to a data block, to sample the analog signals to produce samples, to equalize the samples to produce soft decision bits corresponding to the data block, and to initiate IR operations. The IR processing function is operable to perform IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block. The IR memory operably couples to the IR processing function, includes Type I IR memory adapted to store IR status information of the data block, and includes Type II IR memory adapted to store the data block.
摘要翻译：用于在无线接收机中实现增量冗余（IR）操作的系统包括至少一个处理设备，IR处理功能和IR存储器。所述至少一个处理装置可操作以接收对应于数据块的模拟信号，以对所述模拟信号进行采样以产生样本，以使样本均衡以产生与所述数据块相对应的软判决位，并发起IR操作。 IR处理功能可操作以对数据块的软判决位执行IR操作，以尝试正确解码数据块。 IR存储器可操作地耦合到IR处理功能，包括适于存储数据块的IR状态信息的I型IR存储器，并且包括适于存储数据块的II型IR存储器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式