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1. 发明授权

US09171593B2 Multi-granularity parallel storage system 有权
标题翻译：多粒度并行存储系统
公开(公告)号：US09171593B2
公开(公告)日：2015-10-27
申请号：US14117295
申请日：2011-12-31
申请人： Donglin Wang , Zijun Liu , Xiaojun Xue , Xing Zhang , Zhiwei Zhang , Shaolin Xie
发明人： Donglin Wang , Zijun Liu , Xiaojun Xue , Xing Zhang , Zhiwei Zhang , Shaolin Xie
IPC分类号： G06F12/02 , G11C7/10 , G06F3/06 , G06F12/06 , G11C11/406 , G11C21/00 , G06F9/38
CPC分类号： G11C7/1072 , G06F3/0601 , G06F9/3895 , G06F12/02 , G06F12/0607 , G11C11/40615 , G11C21/00
摘要： A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.
摘要翻译：包括多个存储器，移位发生器，地址增量查找单元，地址移位器，行地址生成器和多个地址加法器的多粒度并行存储系统。移位发生器被配置为产生移位值。地址增量查找单元被配置为生成地址移位器的输入数据。地址移位器被配置为通过Shift元素向右循环移位输入数据，然后输出移位的数据。行地址生成器被配置为生成行地址RowAddr，并将生成的行地址RowAddr输入到每个地址加法器的另一个输入端。每个地址加法器被配置为在两个输入端子处执行输入数据的非符号相加以获得其中一个存储器的读/写（R / W）地址，并将R / W地址输入到地址输入端的记忆。

2. 发明申请

US20140344515A1 MULTI-GRANULARITY PARALLEL STORAGE SYSTEM 有权
标题翻译：多粒度并行存储系统
公开(公告)号：US20140344515A1
公开(公告)日：2014-11-20
申请号：US14117295
申请日：2011-12-31
申请人： Donglin Wang , Zijun Liu , Xiaojun Xue , Xing Zhang , Zhiwei Zhang , Shaolin Xie
发明人： Donglin Wang , Zijun Liu , Xiaojun Xue , Xing Zhang , Zhiwei Zhang , Shaolin Xie
IPC分类号： G11C7/10 , G11C11/406 , G11C21/00
CPC分类号： G11C7/1072 , G06F3/0601 , G06F9/3895 , G06F12/02 , G06F12/0607 , G11C11/40615 , G11C21/00
摘要： A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.
摘要翻译：包括多个存储器，移位发生器，地址增量查找单元，地址移位器，行地址生成器和多个地址加法器的多粒度并行存储系统。移位发生器被配置为产生移位值。地址增量查找单元被配置为生成地址移位器的输入数据。地址移位器被配置为通过Shift元素向右循环移位输入数据，然后输出移位的数据。行地址生成器被配置为生成行地址RowAddr，并将生成的行地址RowAddr输入到每个地址加法器的另一个输入端。每个地址加法器被配置为在两个输入端子处执行输入数据的非符号相加以获得其中一个存储器的读/写（R / W）地址，并将R / W地址输入到地址输入端的记忆。

3. 发明授权

US09099915B2 Congruent power and timing signals for device 有权
标题翻译：设备的一致功率和定时信号
公开(公告)号：US09099915B2
公开(公告)日：2015-08-04
申请号：US13335762
申请日：2011-12-22
申请人： Henry Ge , Welsin Wang , Xing Zhang
发明人： Henry Ge , Welsin Wang , Xing Zhang
IPC分类号： G01R19/00 , H02M7/06 , G01R11/40 , G01R11/42 , H02M1/00
CPC分类号： H02M7/06 , G01R11/40 , G01R11/42 , H02M7/068 , H02M2001/0064
摘要： Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.
摘要翻译：单个电子设备中的一致功率和定时信号。在一个实施例中，电路可以仅包括一个可操作以产生功率信号和定时信号的隔离变压器。在次级侧，两个分支可以提取功率信号和时钟信号，以在隔离次级侧的电路中使用。第一分支可以耦合到变压器并且可操作以将信号操纵成诸如5V DC信号的功率信号。类似地，第二电路支路可操作以将信号操纵成时钟信号，例如频率为1MHz的5V信号。通过从次级侧的同一隔离变压器中提取电源信号和时钟信号，可以在集成电路设备上节省有价值的空间，只需要单个隔离变压器的绕组。

4. 发明授权

US08450155B2 Method for introducing channel stress and field effect transistor fabricated by the same 有权
标题翻译：引入沟道应力的方法和由其制造的场效应晶体管
公开(公告)号：US08450155B2
公开(公告)日：2013-05-28
申请号：US13131602
申请日：2011-04-01
申请人： Ru Huang , Quanxin Yun , Xia An , Xing Zhang
发明人： Ru Huang , Quanxin Yun , Xia An , Xing Zhang
IPC分类号： H01L21/332 , H01L21/335 , H01L21/8232 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/7848 , H01L29/6653 , H01L29/66636 , H01L29/7833 , H01L29/7843
摘要： The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.
摘要翻译：本发明涉及CMOS超大规模集成电路，并且提供了一种引入沟道应力的方法和由其制造的场效应晶体管。根据本发明，应变电介质层介于源极/漏极区域和场效应晶体管的衬底之间，并且通过直接接触衬底的应变介电层在沟道中诱发应变，从而改善信道的载波移动性和设备的性能。本发明的具体效果包括：通过使用具有拉伸应变的应变电介质层，可以在沟道中诱发拉伸应变，以增加通道的电子迁移率; 可以通过使用具有压缩应变的应变电介质层在沟道中诱发压缩应变，以增加通道的空穴迁移率。根据本发明，不仅引入通道应力的有效性，而且基本上也提高了场效应晶体管的器件结构，从而增加了抑制器件的短沟道效应的能力。

5. 发明授权

US08431181B2 Method for surface treating cold cathode 有权
标题翻译：冷阴极表面处理方法
公开(公告)号：US08431181B2
公开(公告)日：2013-04-30
申请号：US12650817
申请日：2009-12-31
申请人： Qi Cai , Tong-Feng Gao , Xing Zhang , Liang Liu , Shou-Shan Fan
发明人： Qi Cai , Tong-Feng Gao , Xing Zhang , Liang Liu , Shou-Shan Fan
IPC分类号： B05D5/06
CPC分类号： H01J9/025 , H01J2201/3043 , H01J2201/30434
摘要： A method for surface treating a cold cathode includes the following steps. A cold cathode is provided and the cold cathode includes a plurality of field emitters. A liquid glue is placed on a surface of the cold cathode. The liquid glue is cured to form solid glue on the surface of the cold cathode. The solid glue is removed to allow the plurality of field emitters to stand upright.
摘要翻译：一种用于表面处理冷阴极的方法包括以下步骤。设置冷阴极，冷阴极包括多个场致发射体。将液体胶放置在冷阴极的表面上。液态胶固化，在冷阴极表面形成固体胶。去除固体胶以允许多个场发射器直立。

6. 发明申请

US20120187495A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120187495A1
公开(公告)日：2012-07-26
申请号：US13201618
申请日：2010-09-25
申请人： Xia An , Yue Guo , Quanxin Yun , Ru Huang , Xing Zhang
发明人： Xia An , Yue Guo , Quanxin Yun , Ru Huang , Xing Zhang
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/16 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.
摘要翻译：本发明提供了一种半导体器件及其制造方法，其中该方法包括：在多个有源区之间提供具有多个有源区和器件隔离区的锗基半导体衬底，其中栅介电层并且栅极电介质层上的栅极设置在有源区上，有源区包括源极和漏极延伸区以及深的源极和漏极区; 对源极和漏极延伸区域执行第一离子注入工艺，其中在第一离子注入工艺中注入的离子包括硅或碳; 对源极和漏极延伸区域执行第二离子注入工艺; 相对于深源极和漏极区域执行第三离子注入工艺; 对已进行第三离子注入工艺的锗基半导体衬底进行退火处理。根据制造半导体器件的方法，通过硅杂质的注入，可以通过栅极和漏极区域中的晶格失配有效地将适当的应力引入锗通道中，使得沟道中电子的迁移率增强并提高了设备的性能。

7. 发明授权

US07990043B2 Field emission cathode structure and field emission display using the same 有权
标题翻译：场发射阴极结构和场发射显示使用相同
公开(公告)号：US07990043B2
公开(公告)日：2011-08-02
申请号：US12695642
申请日：2010-01-28
申请人： Jie Tang , Hai-Yan Hao , Qi Cai , Xing Zhang , Shuai Liu , Bing-Chu Du , Liang Liu , Shou-Shan Fan
发明人： Jie Tang , Hai-Yan Hao , Qi Cai , Xing Zhang , Shuai Liu , Bing-Chu Du , Liang Liu , Shou-Shan Fan
IPC分类号： H01J17/49
CPC分类号： H01J1/304
摘要： A field emission cathode structure includes a dielectric layer, a field emission unit, a grid electrode, and a conductive layer. The dielectric layer is positioned on the insulating substrate and defines a cavity. A field emission unit is attached on the cathode electrode and received in the cavity of the dielectric layer. The field emission unit is electrically attached to the cathode electrode. The grid electrode is located on the dielectric layer, and electrons emitted from the field emission unit emit through the grid electrode. The conductive layer is electrically attached to the grid electrode and insulated from the field emission unit. A field emission display device using the above-mentioned field emission cathode structure is also provided.
摘要翻译：场发射阴极结构包括电介质层，场发射单元，栅电极和导电层。电介质层位于绝缘基片上并限定一个空腔。场致发射单元附着在阴极上并被接收在电介质层的空腔中。场发射单元电连接到阴极电极。栅电极位于电介质层上，从场发射单元发射的电子通过栅电极发射。导电层电连接到栅电极并与场致发射单元绝缘。还提供了使用上述场发射阴极结构的场致发射显示装置。

8. 发明授权

US06522790B1 Method and apparatus for merging images 失效
标题翻译：用于合并图像的方法和装置
公开(公告)号：US06522790B1
公开(公告)日：2003-02-18
申请号：US09407188
申请日：1999-09-28
申请人： Xing Zhang , Jian Zhang
发明人： Xing Zhang , Jian Zhang
IPC分类号： G06K932
CPC分类号： H04N1/3876 , G06T7/32 , G06T7/37
摘要： Two document images which have been compressed using the JBIG-2 standard for facsimile applications so as to include a plurality of index numbers, one or more positions in each image associated with the index numbers, and a group symbol for each index number can be merged to form a final composite image. Firstly, two virtual indexed images are formed by patterns of the index numbers at their associated positions in the document images. The patterns of index numbers in the two virtual indexed images are then compared (22) to determine whether there is correlation between the patterns of index numbers in at least parts of the two virtual indexed images. The two virtual indexed images are then merged (25), when there is a sufficient correlation, such that the parts that correlate overlap each other to provide a merged virtual indexed image, and then the index numbers in the merged virtual indexed image are replaced (7) by the corresponding group symbol to provide the final composite image.
摘要翻译：已经使用用于传真应用的JBIG-2标准压缩的两个文档图像可以被合并以包括多个索引号，与索引号相关联的每个图像中的一个或多个位置以及每个索引号的组符号以形成最终的合成图像。首先，通过在文档图像中的相关位置处的索引号的图案形成两个虚拟索引图像。然后比较（22）两个虚拟索引图像中的索引号的模式，以确定在两个虚拟索引图像的至少部分中的索引号的模式之间是否存在相关性。然后，当存在足够的相关性时，两个虚拟索引图像被合并（25），使得相关的部分彼此重叠以提供合并的虚拟索引图像，然后替换合并的虚拟索引图像中的索引号（ 7）由相应的组符号提供最终的合成图像。

9. 发明授权

US09124152B2 Permanent magnet motor 有权
标题翻译：永磁电机
公开(公告)号：US09124152B2
公开(公告)日：2015-09-01
申请号：US13399647
申请日：2012-02-17
申请人： Mao Xiong Jiang , Yue Li , Jian Zhao , Hong Min Wei , Ke Lin Zhou , Xing Zhang
发明人： Mao Xiong Jiang , Yue Li , Jian Zhao , Hong Min Wei , Ke Lin Zhou , Xing Zhang
IPC分类号： H02K23/04 , H02K5/14 , H02K5/24 , H02K7/116 , H02K13/00
CPC分类号： H02K5/148 , H02K5/24 , H02K7/1166 , H02K13/006
摘要： A permanent magnet motor has a rotor and a stator. The rotor has a shaft, a rotor core and commutator fixed to the shaft, and rotor windings wound about poles of the rotor core and electrically connected to the commutator. The stator has an axially extending round housing, a ring magnet member fixed to an inner surface of the round housing, an endcap, and at least one pair of brushes in sliding contact with the commutator. A chamber is formed by the housing and the endcap. The commutator is disposed in the chamber. A window lift device incorporating the motor is also provided.
摘要翻译：永磁电动机具有转子和定子。转子具有轴，转子芯和固定到轴的换向器，转子绕组缠绕在转子芯的极上并电连接到换向器。定子具有轴向延伸的圆形壳体，固定到圆形壳体的内表面的环形磁体构件，端盖以及与换向器滑动接触的至少一对电刷。一个室由壳体和端盖形成。换向器设置在腔室中。还提供了结合电动机的窗户提升装置。

10. 发明授权

US08673722B2 Strained channel field effect transistor and the method for fabricating the same 有权
标题翻译：应变通道场效应晶体管及其制造方法
公开(公告)号：US08673722B2
公开(公告)日：2014-03-18
申请号：US13255443
申请日：2011-03-23
申请人： Ru Huang , Quanxin Yun , Xia An , Yujie Al , Xing Zhang
发明人： Ru Huang , Quanxin Yun , Xia An , Yujie Al , Xing Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L29/1083 , H01L29/66545 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/7849
摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.
摘要翻译：本发明公开了一种应变通道场效应晶体管及其制造方法。场效应晶体管包括衬底，源极/漏极，栅极电介质层和栅极，其特征在于，“L”形复合隔离层，其包围与源极/漏极相邻的侧面的一部分沟道和源极/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的“L”形绝缘薄层和与源极和漏极直接接触的“L”形高应力层。这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力。

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