专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090271165A1 Simultaneous Parameter-Driven and Deterministic Simulation With or Without Synchronization 有权
标题翻译：具有或不具有同步的同时参数驱动和确定性模拟
公开(公告)号：US20090271165A1
公开(公告)日：2009-10-29
申请号：US12108145
申请日：2008-04-23
申请人： Duane A. Averill , Christopher T. Phan , Corey V. Swenson , Sharon D. Vincent
发明人： Duane A. Averill , Christopher T. Phan , Corey V. Swenson , Sharon D. Vincent
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.
摘要翻译：一种用于在验证硬件设计期间同时进行参数驱动和确定性仿真的方法，包括：使得来自随机指令生成器的多个随机参数驱动命令能够在通过命令管理验证硬件设计的模拟环境中执行设备; 并且通过所述命令管理装置在所述硬件设计的验证期间使得来自手动驱动的测试用例端口的多个确定性命令能够在所述模拟环境中与所述多个随机参数驱动命令同时执行，所述多个确定性命令和所述多个的随机参数驱动命令每个验证硬件设计的功能。

2. 发明授权

US07865854B2 Simultaneous parameter-driven and deterministic simulation with or without synchronization 有权
标题翻译：具有或不具有同步性的同时参数驱动和确定性仿真
公开(公告)号：US07865854B2
公开(公告)日：2011-01-04
申请号：US12108145
申请日：2008-04-23
申请人： Duane A. Averill , Christopher T. Phan , Corey V. Swenson , Sharon D. Vincent
发明人： Duane A. Averill , Christopher T. Phan , Corey V. Swenson , Sharon D. Vincent
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.
摘要翻译：一种用于在验证硬件设计期间同时进行参数驱动和确定性仿真的方法，包括：使得来自随机指令生成器的多个随机参数驱动命令能够在通过命令管理验证硬件设计的模拟环境中执行设备; 并且通过所述命令管理装置在所述硬件设计的验证期间使得来自手动驱动的测试用例端口的多个确定性命令能够在所述模拟环境中与所述多个随机参数驱动命令同时执行，所述多个确定性命令和所述多个的随机参数驱动命令每个验证硬件设计的功能。

3. 发明申请

US20090265534A1 Fairness, Performance, and Livelock Assessment Using a Loop Manager With Comparative Parallel Looping 审中-公开
标题翻译：使用循环管理器进行比较并行循环的公平性，性能和动态锁定评估
公开(公告)号：US20090265534A1
公开(公告)日：2009-10-22
申请号：US12104638
申请日：2008-04-17
申请人： Duane A. Averill , Anthony D. Drumm , Christopher T. Phan , Brian T. Vanderpool , Sharon D. Vincent
发明人： Duane A. Averill , Anthony D. Drumm , Christopher T. Phan , Brian T. Vanderpool , Sharon D. Vincent
IPC分类号： G06F9/30
CPC分类号： G06F9/4881
摘要： A method, apparatus, and computer program are provided for assessing fairness, performance, and livelock in a logic development process utilizing comparative parallel looping. Multiple loop macros are generated, the multiple loop macros respectively correspond to multiple processor threads, and the multiple loop macros are parallel comparative loop macros. The multiple processor threads for the multiple loop macros are executed in which a common resource is accessed. A forward performance of each of the multiple processor threads is verified. The forward performance of the multiple processor threads is compared with each other. It is determined whether any of the multiple processor threads fails to meet a minimum loop count or a minimum loop time. It is determined whether any of the multiple processor threads exceeds a maximum loop count or a maximum loop time. It is recognized whether fairness is maintained during the execution of the multiple processor threads.
摘要翻译：提供了一种方法，装置和计算机程序，用于评估利用比较并行循环的逻辑开发过程中的公平性，性能和活动锁定。生成多个循环宏，多个循环宏分别对应多个处理器线程，多个循环宏是并行的比较循环宏。执行多循环宏的多个处理器线程，其中访问公共资源。验证多个处理器线程中的每一个的前向性能。将多个处理器线程的前向性能相互比较。确定多个处理器线程中的任何一个线程是否不能满足最小循环计数或最小循环时间。确定多个处理器线程中的任何一个线程是否超过最大循环计数或最大循环时间。公认在执行多个处理器线程期间是否保持公平性。

4. 发明申请

US20080262821A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY MANAGING SIMULATED ADDRESSES 审中-公开
标题翻译：用于动态管理模拟地址的方法，装置和计算机程序产品
公开(公告)号：US20080262821A1
公开(公告)日：2008-10-23
申请号：US11737297
申请日：2007-04-19
申请人： Christopher T. Phan , Sharon D. Vincent
发明人： Christopher T. Phan , Sharon D. Vincent
IPC分类号： G06F9/44
CPC分类号： G06F17/5022
摘要： A method, apparatus, and computer program product are provided for dynamically generating and managing addresses in a simulation environment. Address parameters and requests for addresses for performing commands from multiple simulation components are received. The multiple simulation components are associated with address maps. The requests include configuration parameters. Addresses are provided for performing the commands at the multiple simulation components based on the address parameters and the configuration parameters. Address generation is centrally managed such that when an address map for one simulation component changes, address maps associated with other simulation components and access to the other simulation components are not affected.
摘要翻译：提供了一种用于在模拟环境中动态生成和管理地址的方法，装置和计算机程序产品。接收来自多个模拟组件的地址参数和用于执行命令的地址请求。多个模拟组件与地址映射关联。请求包括配置参数。提供地址，用于根据地址参数和配置参数在多个仿真组件执行命令。地址生成被集中管理，使得当一个仿真组件的地址映射更改时，与其他仿真组件相关联的地址映射和对其他仿真组件的访问不受影响。

5. 发明授权

US09021483B2 Making hardware objects and operations thread-safe 有权
标题翻译：使硬件对象和操作线程安全
公开(公告)号：US09021483B2
公开(公告)日：2015-04-28
申请号：US12430214
申请日：2009-04-27
申请人： Daniel M. Crowell , Alan Hlava , Christopher T. Phan , David D. Sanner
发明人： Daniel M. Crowell , Alan Hlava , Christopher T. Phan , David D. Sanner
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/526
摘要： Performance in object-oriented systems may be improved by allowing multiple concurrent hardware control and diagnostic operations to run concurrently on the system while preventing race conditions, state/data corruption, and hangs due to deadlock conditions. Deadlock prevention rules may be employed to grant or deny request for hardware operation locks, hardware communication locks, and/or data locks.
摘要翻译：可以通过允许多个并发硬件控制和诊断操作同时在系统上运行，同时防止由于死锁条件引起的竞争条件，状态/数据损坏和挂起，从而可以改善面向对象系统中的性能。可以采用防止死锁规则来授予或拒绝对硬件操作锁，硬件通信锁和/或数据锁的请求。

6. 发明申请

US20100275216A1 Making Hardware Objects and Operations Thread-Safe 有权
标题翻译：使硬件对象和操作线程安全
公开(公告)号：US20100275216A1
公开(公告)日：2010-10-28
申请号：US12430214
申请日：2009-04-27
申请人： Daniel M. Crowell , Alan Hlava , Christopher T. Phan , David D. Sanner
发明人： Daniel M. Crowell , Alan Hlava , Christopher T. Phan , David D. Sanner
IPC分类号： G06F9/46
CPC分类号： G06F9/526
摘要： Performance in object-oriented systems may be improved by allowing multiple concurrent hardware control and diagnostic operations to run concurrently on the system while preventing race conditions, state/data corruption, and hangs due to deadlock conditions. Deadlock prevention rules may be employed to grant or deny request for hardware operation locks, hardware communication locks, and/or data locks.
摘要翻译：可以通过允许多个并发硬件控制和诊断操作同时在系统上运行，同时防止由于死锁条件引起的竞争条件，状态/数据损坏和挂起，从而可以改善面向对象系统中的性能。可以采用防止死锁规则来授予或拒绝对硬件操作锁，硬件通信锁和/或数据锁的请求。

7. 发明申请

US20080010321A1 METHOD AND SYSTEM FOR COHERENT DATA CORRECTNESS CHECKING USING A GLOBAL VISIBILITY AND PERSISTENT MEMORY MODEL 审中-公开
标题翻译：使用全局可见性和持久记忆模型进行相关数据正确检查的方法和系统
公开(公告)号：US20080010321A1
公开(公告)日：2008-01-10
申请号：US11425239
申请日：2006-06-20
申请人： Christopher T. Phan , Jamie R. Kuesel
发明人： Christopher T. Phan , Jamie R. Kuesel
IPC分类号： G06F17/30 , G06F12/00
CPC分类号： G06F12/0815 , G06F2212/1032
摘要： Exemplary embodiments include a system for coherent data correctness checking including: an address manager in operable communication with a processor, a DRAM model, and a IO bus; and a persistent memory model in operable communication with the processor, the IO bus, and a unit monitor checker, the persistent memory model operable for storing data information that can be compared with a data stored in an internal cache of the processor or the DRAM, wherein the unit monitor checker tracks memory operations throughout the system.
摘要翻译：示例性实施例包括用于相干数据正确性检查的系统，其包括：与处理器可操作地通信的地址管理器，DRAM模型和IO总线; 以及与处理器，IO总线和单元监视器检查器可操作地通信的持久存储器模型，持续存储器模型可操作用于存储可与存储在处理器或DRAM的内部高速缓存中的数据进行比较的数据信息，其中单元监视器检查器跟踪整个系统中的存储器操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式