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1. 发明授权

US07865854B2 Simultaneous parameter-driven and deterministic simulation with or without synchronization 有权
标题翻译：具有或不具有同步性的同时参数驱动和确定性仿真
公开(公告)号：US07865854B2
公开(公告)日：2011-01-04
申请号：US12108145
申请日：2008-04-23
申请人： Duane A. Averill , Christopher T. Phan , Corey V. Swenson , Sharon D. Vincent
发明人： Duane A. Averill , Christopher T. Phan , Corey V. Swenson , Sharon D. Vincent
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.
摘要翻译：一种用于在验证硬件设计期间同时进行参数驱动和确定性仿真的方法，包括：使得来自随机指令生成器的多个随机参数驱动命令能够在通过命令管理验证硬件设计的模拟环境中执行设备; 并且通过所述命令管理装置在所述硬件设计的验证期间使得来自手动驱动的测试用例端口的多个确定性命令能够在所述模拟环境中与所述多个随机参数驱动命令同时执行，所述多个确定性命令和所述多个的随机参数驱动命令每个验证硬件设计的功能。

2. 发明申请

US20090271165A1 Simultaneous Parameter-Driven and Deterministic Simulation With or Without Synchronization 有权
标题翻译：具有或不具有同步的同时参数驱动和确定性模拟
公开(公告)号：US20090271165A1
公开(公告)日：2009-10-29
申请号：US12108145
申请日：2008-04-23
申请人： Duane A. Averill , Christopher T. Phan , Corey V. Swenson , Sharon D. Vincent
发明人： Duane A. Averill , Christopher T. Phan , Corey V. Swenson , Sharon D. Vincent
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.
摘要翻译：一种用于在验证硬件设计期间同时进行参数驱动和确定性仿真的方法，包括：使得来自随机指令生成器的多个随机参数驱动命令能够在通过命令管理验证硬件设计的模拟环境中执行设备; 并且通过所述命令管理装置在所述硬件设计的验证期间使得来自手动驱动的测试用例端口的多个确定性命令能够在所述模拟环境中与所述多个随机参数驱动命令同时执行，所述多个确定性命令和所述多个的随机参数驱动命令每个验证硬件设计的功能。

3. 发明申请

US20090265534A1 Fairness, Performance, and Livelock Assessment Using a Loop Manager With Comparative Parallel Looping 审中-公开
标题翻译：使用循环管理器进行比较并行循环的公平性，性能和动态锁定评估
公开(公告)号：US20090265534A1
公开(公告)日：2009-10-22
申请号：US12104638
申请日：2008-04-17
申请人： Duane A. Averill , Anthony D. Drumm , Christopher T. Phan , Brian T. Vanderpool , Sharon D. Vincent
发明人： Duane A. Averill , Anthony D. Drumm , Christopher T. Phan , Brian T. Vanderpool , Sharon D. Vincent
IPC分类号： G06F9/30
CPC分类号： G06F9/4881
摘要： A method, apparatus, and computer program are provided for assessing fairness, performance, and livelock in a logic development process utilizing comparative parallel looping. Multiple loop macros are generated, the multiple loop macros respectively correspond to multiple processor threads, and the multiple loop macros are parallel comparative loop macros. The multiple processor threads for the multiple loop macros are executed in which a common resource is accessed. A forward performance of each of the multiple processor threads is verified. The forward performance of the multiple processor threads is compared with each other. It is determined whether any of the multiple processor threads fails to meet a minimum loop count or a minimum loop time. It is determined whether any of the multiple processor threads exceeds a maximum loop count or a maximum loop time. It is recognized whether fairness is maintained during the execution of the multiple processor threads.
摘要翻译：提供了一种方法，装置和计算机程序，用于评估利用比较并行循环的逻辑开发过程中的公平性，性能和活动锁定。生成多个循环宏，多个循环宏分别对应多个处理器线程，多个循环宏是并行的比较循环宏。执行多循环宏的多个处理器线程，其中访问公共资源。验证多个处理器线程中的每一个的前向性能。将多个处理器线程的前向性能相互比较。确定多个处理器线程中的任何一个线程是否不能满足最小循环计数或最小循环时间。确定多个处理器线程中的任何一个线程是否超过最大循环计数或最大循环时间。公认在执行多个处理器线程期间是否保持公平性。

4. 发明授权

US08028128B2 Method for increasing cache directory associativity classes in a system with a register space memory 有权
标题翻译：在具有寄存器空间存储器的系统中增加缓存目录关联类的方法
公开(公告)号：US08028128B2
公开(公告)日：2011-09-27
申请号：US11869901
申请日：2007-10-10
申请人： Duane A. Averill , Herman L. Blackmon , Joseph A. Kirscht , David A. Shedivy
发明人： Duane A. Averill , Herman L. Blackmon , Joseph A. Kirscht , David A. Shedivy
IPC分类号： G06F12/00
CPC分类号： G06F12/0895
摘要： In a method of managing a cache directory in a memory system, an original system address is presented to the cache directory when corresponding associativity data is allocated to an associativity class in the cache directory. The original system address is normalized by removing address space corresponding to a memory hole, thereby generating a normalized address. The normalized address is stored in the cache directory. The normalized address is de-normalized, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for new associativity data. The de-normalized address is sent to the memory system for coherency management.
摘要翻译：在管理存储器系统中的高速缓存目录的方法中，当将相应的关联性数据分配给高速缓存目录中的关联性类时，将原始系统地址呈现给高速缓存目录。原始系统地址通过移除与存储器孔对应的地址空间进行归一化，从而生成归一化地址。归一化地址存储在缓存目录中。归一化地址被去标准化，从而当关联性数据被推出高速缓存目录以为新的关联数据腾出空间时，生成去归一化的地址。将去规范化的地址发送到存储器系统以进行一致性管理。

5. 发明授权

US07925857B2 Method for increasing cache directory associativity classes via efficient tag bit reclaimation 失效
标题翻译：通过高效标签位回收来增加缓存目录关联类的方法
公开(公告)号：US07925857B2
公开(公告)日：2011-04-12
申请号：US12019068
申请日：2008-01-24
申请人： Duane A. Averill , Herman L. Blackmon , Joseph A. Kirscht , David A. Shedivy
发明人： Duane A. Averill , Herman L. Blackmon , Joseph A. Kirscht , David A. Shedivy
IPC分类号： G06F13/00
CPC分类号： G06F12/0864 , G06F12/0817
摘要： In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address tag is configured to store a unique address to a specific location in an memory space. An amount of memory that is in an actually configured portion of the memory space is determined. A minimum number of bits necessary to address each memory location in the actually configured portion of the memory space is determined. Each address tag is configured in each associativity class to include the minimum number of bits necessary to address each memory location in the actually configured portion of the memory space. The cache directory is configured to include a maximum number of associativity classes per line in the cache directory.
摘要翻译：在生成包括多个关联类的高速缓存目录的方法中，每个关联性类包括包括多个地址位的地址标签。每个地址标签被配置为将唯一地址存储到存储器空间中的特定位置。确定存储器空间的实际配置部分中的存储器量。确定对存储器空间的实际配置的部分中的每个存储器位置进行寻址所需的最小位数。每个地址标签被配置在每个关联性类中，以包括为存储器空间的实际配置的部分中的每个存储器位置所需的最小位数。缓存目录被配置为在缓存目录中包括每行最大数量的关联类。

6. 发明申请

US20090193199A1 Method for Increasing Cache Directory Associativity Classes Via Efficient Tag Bit Reclaimation 失效
标题翻译：通过有效的标记位回收增加缓存目录关联类的方法
公开(公告)号：US20090193199A1
公开(公告)日：2009-07-30
申请号：US12019068
申请日：2008-01-24
申请人： Duane A. Averill , Herman L. Blackmon , Joseph A. Kirscht , David A. Shedivy
发明人： Duane A. Averill , Herman L. Blackmon , Joseph A. Kirscht , David A. Shedivy
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0817
摘要： In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address tag is configured to store a unique address to a specific location in an memory space. An amount of memory that is in an actually configured portion of the memory space is determined. A minimum number of bits necessary to address each memory location in the actually configured portion of the memory space is determined. Each address tag is configured in each associativity class to include the minimum number of bits necessary to address each memory location in the actually configured portion of the memory space. The cache directory is configured to include a maximum number of associativity classes per line in the cache directory.
摘要翻译：在生成包括多个关联类的高速缓存目录的方法中，每个关联性类包括包括多个地址位的地址标签。每个地址标签被配置为将唯一地址存储到存储器空间中的特定位置。确定存储器空间的实际配置部分中的存储器量。确定对存储器空间的实际配置的部分中的每个存储器位置进行寻址所需的最小位数。每个地址标签被配置在每个关联性类中，以包括为存储器空间的实际配置的部分中的每个存储器位置寻址所需的最小位数。缓存目录被配置为在缓存目录中包括每行最大数量的关联类。

7. 发明申请

US20090100229A1 Method for Increasing Cache Directory Associativity Classes in a System With a Register Space Memory 有权
标题翻译：用于增加具有寄存器空间存储器的系统中的缓存目录关联类的方法
公开(公告)号：US20090100229A1
公开(公告)日：2009-04-16
申请号：US11869901
申请日：2007-10-10
申请人： Duane A. Averill , Herman L. Blackmon , Joseph A. Kirscht , David A. Shedivy
发明人： Duane A. Averill , Herman L. Blackmon , Joseph A. Kirscht , David A. Shedivy
IPC分类号： G06F12/00
CPC分类号： G06F12/0895
摘要： In a method of managing a cache directory in a memory system, an original system address is presented to the cache directory when corresponding associativity data is allocated to an associativity class in the cache directory. The original system address is normalized by removing address space corresponding to a memory hole, thereby generating a normalized address. The normalized address is stored in the cache directory. The normalized address is de-normalized, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for new associativity data. The de-normalized address is sent to the memory system for coherency management.
摘要翻译：在管理存储器系统中的高速缓存目录的方法中，当将相应的关联性数据分配给高速缓存目录中的关联性类时，将原始系统地址呈现给高速缓存目录。原始系统地址通过移除与存储器孔对应的地址空间进行归一化，从而生成归一化地址。归一化地址存储在缓存目录中。归一化地址被去标准化，从而当关联性数据被推出高速缓存目录以为新的关联数据腾出空间时，生成去归一化的地址。将去规范化的地址发送到存储器系统以进行一致性管理。

8. 发明授权

US6088788A Background completion of instruction and associated fetch request in a multithread processor 失效
标题翻译：在多线程处理器中完成指令和相关的提取请求
公开(公告)号：US6088788A
公开(公告)日：2000-07-11
申请号：US773572
申请日：1996-12-27
申请人： John M. Borkenhagen , Richard J. Eickemeyer , Sheldon B. Levenstein , Andrew H. Wottreng , Duane A. Averill , James I. Brookhouser
发明人： John M. Borkenhagen , Richard J. Eickemeyer , Sheldon B. Levenstein , Andrew H. Wottreng , Duane A. Averill , James I. Brookhouser
IPC分类号： G06F9/38 , G06F9/40 , G06F15/76
CPC分类号： G06F9/3851 , G06F9/3824
摘要： The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled. After the requested data returns from higher level memory, the storage control unit will dispatch the instruction from the first thread having received the cache miss to an unused slot in the storage pipeline. Consequently, this instruction from the first thread will be processed along with the instructions from the second thread.
摘要翻译：数据处理系统包括形成多个处理流水线的多个执行单元。多个处理管线处理指令并且包括存储管线。数据处理系统还包括指令单元和存储控制单元。指令单元向多个执行单元输出指令，并且控制多个执行单元执行多个线程。如果存储管线中的第一线程的指令经历高速缓存未命中并且指令单元决定切换线程，则指令单元开始处理第二线程。指令单元还向存储控制单元发出数据请求以获得丢失的数据。在处理第二个线程期间，未使用的插槽将出现在存储管道中，因为不可能总是调度指令以完全保持管道的填充。在所请求的数据从较高级存储器返回之后，存储控制单元将从接收到高速缓存未命中的第一线程的指令发送到存储流水线中的未使用的时隙。因此，来自第一个线程的指令将与第二个线程的指令一起处理。

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