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    • 1. 发明授权
    • Packing trace protocols within trace streams
    • 跟踪流中包装跟踪协议
    • US08001428B2
    • 2011-08-16
    • US12289404
    • 2008-10-27
    • Edmond John Simon AshfieldAndrew Brookfield Swaine
    • Edmond John Simon AshfieldAndrew Brookfield Swaine
    • G06F11/00
    • G06F11/3466G06F11/348
    • A data processing apparatus is provided with packing circuitry 130 arranged to receive said source data elements from said trace data receiver and applies a packing protocol to said source data elements to pack data of source data elements of a source trace stream into a packed trace data stream for supply to trace accepting circuitry in a format comprising acceptance data elements. The acceptance data elements have a bit-length that is not a factor of the source data element bit-length. In some arrangements the source data elements are non byte-sized data elements. In alternative arrangements, the packing circuitry packs a first positive integer number of source data elements into a data chunk comprising a second, different positive integer number of acceptance data elements. In further alternative arrangements the source trace protocol has a variable packet size and the data chunk is formed from a first portion comprising data of the source data elements and a further portion comprising a size-indicating code.
    • 数据处理装置设置有打包电路130,打包电路130被布置为从所述跟踪数据接收器接收所述源数据元素,并且将打包协议应用于所述源数据元素以将源跟踪流的源数据元素的数据打包成压缩跟踪数据流 用于以包含接受数据元素的格式提供到跟踪接收电路。 接受数据元素具有不是源数据元素位长度的因子的位长度。 在一些布置中,源数据元素是非字节大小的数据元素。 在替代布置中,打包电路将第一正整数数量的源数据元素封装到包括第二不同的正整数个接受数据元素的数据块中。 在另外的替代布置中,源跟踪协议具有可变分组大小,并且数据块由包括源数据元素的数据的第一部分和包括大小指示代码的另外部分形成。
    • 2. 发明申请
    • Packing trace protocols within trace streams
    • 跟踪流中包装跟踪协议
    • US20090132863A1
    • 2009-05-21
    • US12289404
    • 2008-10-27
    • Edmond John Simon AshfieldAndrew Brookfield Swaine
    • Edmond John Simon AshfieldAndrew Brookfield Swaine
    • G06F11/00G06F11/32
    • G06F11/3466G06F11/348
    • A data processing apparatus is provided with packing circuitry 130 arranged to receive said source data elements from said trace data receiver and applies a packing protocol to said source data elements to pack data of source data elements of a source trace stream into a packed trace data stream for supply to trace accepting circuitry in a format comprising acceptance data elements. The acceptance data elements have a bit-length that is not a factor of the source data element bit-length. In some arrangements the source data elements are non byte-sized data elements. In alternative arrangements, the packing circuitry packs a first positive integer number of source data elements into a data chunk comprising a second, different positive integer number of acceptance data elements. In further alternative arrangements the source trace protocol has a variable packet size and the data chunk is formed from a first portion comprising data of the source data elements and a further portion comprising a size-indicating code.
    • 数据处理装置设置有打包电路130,打包电路130被布置为从所述跟踪数据接收器接收所述源数据元素,并且将打包协议应用于所述源数据元素以将源跟踪流的源数据元素的数据打包成压缩跟踪数据流 用于以包含接受数据元素的格式提供到跟踪接收电路。 接受数据元素具有不是源数据元素位长度的因子的位长度。 在一些布置中,源数据元素是非字节大小的数据元素。 在替代布置中,打包电路将第一正整数数量的源数据元素封装到包括第二不同的正整数个接受数据元素的数据块中。 在另外的替代布置中,源跟踪协议具有可变分组大小,并且数据块由包括源数据元素的数据的第一部分和包括大小指示代码的另外部分形成。
    • 6. 发明申请
    • Controlling complex non-linear data transfers
    • 控制复杂的非线性数据传输
    • US20080201494A1
    • 2008-08-21
    • US11707275
    • 2007-02-16
    • Paul KimelmanEdmond John Simon AshfieldSteven Richard MellorIan Field
    • Paul KimelmanEdmond John Simon AshfieldSteven Richard MellorIan Field
    • G06F13/28
    • G06F13/28
    • A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.
    • 公开了一种用于控制多个数据源与多个数据目的地之间的数据传输的直接存储器存取控制器。 多个数据源和数据目的地经由多个通道与直接存储器访问控制器通信,直接存储器访问控制器还与存储器和处理器进行通信。 存储器存储用于多个通道中的每个通道和处理器的两组控制数据。 直接存储器存取控制器响应于从所述多个通道中的一个或从所述处理器接收的数据传输请求,以访问存储在所述存储器中的一组所述对应控制数据,所述直接存储器访问执行所述数据的至少一部分 根据所访问的控制数据请求传送。
    • 8. 发明授权
    • Controlling complex non-linear data transfers
    • 控制复杂的非线性数据传输
    • US08112560B2
    • 2012-02-07
    • US12805913
    • 2010-08-24
    • Paul KimelmanEdmond John Simon AshfieldSteven Richard MellorIan Field
    • Paul KimelmanEdmond John Simon AshfieldSteven Richard MellorIan Field
    • G06F13/28G06F13/36
    • G06F13/28
    • A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.
    • 公开了一种用于控制多个数据源与多个数据目的地之间的数据传输的直接存储器存取控制器。 多个数据源和数据目的地经由多个通道与直接存储器访问控制器通信,直接存储器访问控制器还与存储器和处理器进行通信。 存储器存储用于多个通道中的每个通道和处理器的两组控制数据。 直接存储器存取控制器响应于从所述多个通道中的一个或从所述处理器接收的数据传输请求,以访问存储在所述存储器中的一组所述对应控制数据,所述直接存储器访问执行所述数据的至少一部分 根据所访问的控制数据请求传送。