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1. 发明申请

US20120280732A1 APPARATUS, SYSTEM, AND METHOD FOR VOLTAGE SWING AND DUTY CYCLE ADJUSTMENT 有权
标题翻译：用于电压摆幅和占空比调整的装置，系统和方法
公开(公告)号：US20120280732A1
公开(公告)日：2012-11-08
申请号：US13100669
申请日：2011-05-04
申请人： Eduard Roytman , Jian Xu , Rahul R. Shah , Kambiz R. Munshi , Ronald L. Bedard , Mahalingam Nagarajan
发明人： Eduard Roytman , Jian Xu , Rahul R. Shah , Kambiz R. Munshi , Ronald L. Bedard , Mahalingam Nagarajan
IPC分类号： H03K3/017
CPC分类号： H03K5/086 , H03K5/1565 , H03M1/004 , H03M1/126 , H03M1/50
摘要： Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.
摘要翻译：这里描述了一种用于通过调整信号的电压摆幅和占空比来补偿处理器的输入输出（I / O）焊盘上的信号的电压摆幅和占空比的装置，系统和方法。该装置包括用于在I / O焊盘上传输信号的驱动器，I / O焊盘上的信号具有电压摆幅和占空比; 以及耦合到驱动器的调整单元，用于接收由驱动器发送的I / O焊盘的信号，并产生用于调整I / O上信号的电压摆幅和占空比的电压摆幅和占空比控制信号垫分别。这里描述的也是用于测量和/或校准包括电流，电压和时间的各种信号属性的模数（A2D）转换器。

2. 发明授权

US08542046B2 Apparatus, system, and method for voltage swing and duty cycle adjustment 有权
公开(公告)号：US08542046B2
公开(公告)日：2013-09-24
申请号：US13100669
申请日：2011-05-04
申请人： Eduard Roytman , Jian Xu , Rahul R. Shah , Kambiz R. Munshi , Ronald L. Bedard , Mahalingam Nagarajan
发明人： Eduard Roytman , Jian Xu , Rahul R. Shah , Kambiz R. Munshi , Ronald L. Bedard , Mahalingam Nagarajan
IPC分类号： H03K3/017
CPC分类号： H03K5/086 , H03K5/1565 , H03M1/004 , H03M1/126 , H03M1/50
摘要： Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.

3. 发明授权

US09160320B2 Apparatus, system, and method for voltage swing and duty cycle adjustment 有权
标题翻译：用于电压摆幅和占空比调整的装置，系统和方法
公开(公告)号：US09160320B2
公开(公告)日：2015-10-13
申请号：US14035782
申请日：2013-09-24
申请人： Eduard Roytman , Jian Xu , Rahul Shah , Kambiz R. Munshi , Ronald L. Bedard , Mahalingam Nagarajan
发明人： Eduard Roytman , Jian Xu , Rahul Shah , Kambiz R. Munshi , Ronald L. Bedard , Mahalingam Nagarajan
IPC分类号： H03M1/12 , H03M1/50 , H03K5/08 , H03M1/00 , H03K5/156
CPC分类号： H03K5/086 , H03K5/1565 , H03M1/004 , H03M1/126 , H03M1/50
摘要： Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time.
摘要翻译：这里描述了一种用于通过调整信号的电压摆幅和占空比来补偿处理器的输入输出（I / O）焊盘上的信号的电压摆幅和占空比的装置，系统和方法。该装置包括用于在I / O焊盘上传输信号的驱动器，I / O焊盘上的信号具有电压摆幅和占空比; 以及耦合到驱动器的调整单元，用于接收由驱动器发送的I / O焊盘的信号，并产生用于调整I / O上信号的电压摆幅和占空比的电压摆幅和占空比控制信号垫分别。这里描述的也是用于测量和/或校准包括电流，电压和时间的各种信号属性的模数（A2D）转换器。

4. 发明授权

US09319039B2 Forwarded clock jitter reduction 有权
标题翻译：转发时钟抖动减少
公开(公告)号：US09319039B2
公开(公告)日：2016-04-19
申请号：US13976877
申请日：2011-12-30
申请人： Eduard Roytman , Mahalingam Nagarajan , Pradeep R. Vempada
发明人： Eduard Roytman , Mahalingam Nagarajan , Pradeep R. Vempada
IPC分类号： H03K3/017 , H03K5/156 , H03K5/26 , H04L25/02 , H04L25/03
CPC分类号： H03K5/1565 , H03F3/45071 , H03F2200/144 , H03F2200/165 , H03F2200/375 , H03F2200/78 , H03K5/26 , H04L25/0274 , H04L25/0296 , H04L25/03878
摘要： In some embodiments, a differential amplifier with duty cycle correction is provided.
摘要翻译：在一些实施例中，提供了具有占空比校正的差分放大器。

5. 发明授权

US07570704B2 Transmitter architecture for high-speed communications 有权
标题翻译：用于高速通信的发射机架构
公开(公告)号：US07570704B2
公开(公告)日：2009-08-04
申请号：US11290860
申请日：2005-11-30
申请人： Mahalingam Nagarajan , Eduard Roytman
发明人： Mahalingam Nagarajan , Eduard Roytman
IPC分类号： H04L27/00 , G06F17/10
CPC分类号： H04L25/03038 , H03M1/0682 , H03M1/745 , H04L2025/03471
摘要： A transmitter architecture includes an equalizer and a D/A converter, for high-speed transmission of data across a channel. The equalizer includes a two-tap MAC as part of an N-stage, two-way interleaved FIR filter. The two-tap MAC provides substantial power and area savings over conventional MAC-based FIR filter designs, and may be implemented in short or long communications channels. The D/A converter is decoupled from the equalizer. Its N-bit, binary-weighted driver includes matched unit current generation cells, all of which are fully utilized during each digital-to-analog conversion. The D/A converter remains unchanged, even when the characteristics of the equalizer are changed.
摘要翻译：发射机架构包括均衡器和D / A转换器，用于通过信道的高速数据传输。均衡器包括两抽头MAC作为N级双向交错FIR滤波器的一部分。两抽头MAC比传统的基于MAC的FIR滤波器设计提供了实质的功率和面积节省，并且可以在短或长的通信信道中实现。 D / A转换器与均衡器去耦。其N位二进制加权驱动器包括匹配的单位电流产生单元，所有这些单元在每个数模转换期间都得到充分利用。即使改变均衡器的特性，D / A转换器也保持不变。

6. 发明申请

US20130285726A1 FORWARDED CLOCK JITTER REDUCTION 有权
标题翻译：前进的时钟抖动减少
公开(公告)号：US20130285726A1
公开(公告)日：2013-10-31
申请号：US13976877
申请日：2011-12-30
申请人： Eduard Roytman , Mahalingam Nagarajan , Pradeep R. Vempada
发明人： Eduard Roytman , Mahalingam Nagarajan , Pradeep R. Vempada
IPC分类号： H03K5/156
CPC分类号： H03K5/1565 , H03F3/45071 , H03F2200/144 , H03F2200/165 , H03F2200/375 , H03F2200/78 , H03K5/26 , H04L25/0274 , H04L25/0296 , H04L25/03878
摘要： In some embodiments, a differential amplifier with duty cycle correction is provided.
摘要翻译：在一些实施例中，提供了具有占空比校正的差分放大器。

7. 发明申请

US20070121716A1 Novel transmitter architecture for high-speed communications 有权
标题翻译：用于高速通信的新型发射机架构
公开(公告)号：US20070121716A1
公开(公告)日：2007-05-31
申请号：US11290860
申请日：2005-11-30
申请人： Mahalingam Nagarajan , Eduard Roytman
发明人： Mahalingam Nagarajan , Eduard Roytman
IPC分类号： H03M1/66 , H03H7/30 , H04L27/00
CPC分类号： H04L25/03038 , H03M1/0682 , H03M1/745 , H04L2025/03471
摘要： A transmitter architecture includes an equalizer and a D/A converter, for high-speed transmission of data across a channel. The equalizer includes a two-tap MAC as part of an N-stage, two-way interleaved FIR filter. The two-tap MAC provides substantial power and area savings over conventional MAC-based FIR filter designs, and may be implemented in short or long communications channels. The D/A converter is decoupled from the equalizer. Its N-bit, binary-weighted driver includes matched unit current generation cells, all of which are fully utilized during each digital-to-analog conversion. The D/A converter remains unchanged, even when the characteristics of the equalizer are changed.
摘要翻译：发射机架构包括均衡器和D / A转换器，用于通过信道的高速数据传输。均衡器包括两抽头MAC作为N级双向交错FIR滤波器的一部分。两抽头MAC比传统的基于MAC的FIR滤波器设计提供了实质的功率和面积节省，并且可以在短或长的通信信道中实现。 D / A转换器与均衡器去耦。其N位二进制加权驱动器包括匹配的单位电流产生单元，所有这些单元在每个数模转换期间都得到充分利用。即使改变均衡器的特性，D / A转换器也保持不变。

8. 发明授权

US07332947B2 Method and apparatus for distorting duty cycle of a clock 有权
标题翻译：用于扭曲时钟占空比的方法和装置
公开(公告)号：US07332947B2
公开(公告)日：2008-02-19
申请号：US11082142
申请日：2005-03-15
申请人： Arvind Kumar , Narayanan Natarajan , Mahalingam Nagarajan
发明人： Arvind Kumar , Narayanan Natarajan , Mahalingam Nagarajan
IPC分类号： H03L7/06
CPC分类号： G06F1/04 , H03K5/1565
摘要： An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described.
摘要翻译：公开了一种用于可控地扭曲时钟信号的占空比的装置。还描述了使用本发明的实施例的方法和系统。

9. 发明申请

US20060208781A1 Method and apparatus for distorting duty cycle of a clock 有权
标题翻译：用于扭曲时钟占空比的方法和装置
公开(公告)号：US20060208781A1
公开(公告)日：2006-09-21
申请号：US11082142
申请日：2005-03-15
申请人： Arvind Kumar , Narayanan Natarajan , Mahalingam Nagarajan
发明人： Arvind Kumar , Narayanan Natarajan , Mahalingam Nagarajan
IPC分类号： H03K3/017
CPC分类号： G06F1/04 , H03K5/1565
摘要： An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described.
摘要翻译：公开了一种用于可控地扭曲时钟信号的占空比的装置。还描述了使用本发明的实施例的方法和系统。

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