专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120224657A1 CARRIER RECOVERY CIRCUIT AND DEMODULATION CIRCUIT UNDER QUASI-COHERENT DETECTION METHOD 失效
标题翻译：基于相关检测方法的载波恢复电路和解调电路
公开(公告)号：US20120224657A1
公开(公告)日：2012-09-06
申请号：US13505346
申请日：2010-11-05
申请人： Eisaku Sasaki , Hirotaka Sato
发明人： Eisaku Sasaki , Hirotaka Sato
IPC分类号： H04L27/22
CPC分类号： H04L27/2273 , H04L27/3827 , H04L2027/0057 , H04L2027/0069 , H04L2027/0081
摘要： A carrier recovery circuit, adapted to a demodulation circuit according to a quasi-coherent detection method for generating baseband signals by way of quadrature detection on a received signal having an intermediate frequency, rotates phases of baseband signals; detects a phase error and an amplitude error; controls a bandwidth of a loop filter based on its difference, eliminates a high-frequency component from the phase error; and performs phase rotation based on the phase error eliminating its high-frequency component. It expands the bandwidth of the loop filter when a difference between the phase error and the amplitude error is greater than a predetermined threshold, whilst reducing bandwidth of the loop filter upon determining that the amplitude error decreases due to a reduction of the bandwidth of the loop filter. This optimizes the bandwidth of the loop filter to follow variations of the C/N ratio of the received signal, improving bit error rate.
摘要翻译：根据用于通过对具有中频的接收信号进行正交检测来生成基带信号的准相干检测方法的解调电路的载波恢复电路，旋转基带信号的相位; 检测相位误差和振幅误差; 基于其差异来控制环路滤波器的带宽，从相位误差中消除高频分量; 并根据消除其高频分量的相位误差进行相位旋转。当相位误差和幅度误差之间的差异大于预定阈值时，扩展环路滤波器的带宽，同时在由于环路带宽的降低导致振幅误差减小时减小环路滤波器的带宽过滤。这优化了环路滤波器的带宽，以遵循接收信号的C / N比的变化，从而提高误码率。

2. 发明授权

US6127897A Zero-crossing detection type clock recovery circuit operated at symbol rate 失效
标题翻译：过零检测型时钟恢复电路以符号速率运行
公开(公告)号：US6127897A
公开(公告)日：2000-10-03
申请号：US362491
申请日：1999-07-28
申请人： Eisaku Sasaki
发明人： Eisaku Sasaki
IPC分类号： H04L7/00 , H04L7/033 , H04L27/38 , H03D3/00
CPC分类号： H04L7/0334 , H04L27/38
摘要： In a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system, an analog/digital (A/D) converter performs an A/D conversion upon an analog baseband signal in synchronization with a sampling clock signal having a time period that is a symbol time period. A phase detector receives successive first and third data sampled from the A/D converter, calculates second data by addition of the first and third data, determines whether or not a signal transition formed by the first and third data crosses a zero value within a predetermined deviation, and compares a polarity of the second data with a polarity of one of the first and third data, and generates a comparison result as a phase detection signal when the signal transition crosses the zero value. A loop filter passes a low-frequency component of the phase detection signal therethrough. A voltage controlled oscillator supplies the sampling clock signal to the A/D converter in accordance with an output signal of the loop filter.
摘要翻译：在多电平正交幅度调制（QAM）系统的解调器中的时钟恢复电路中，模数/数字（A / D）转换器与模拟基带信号同时进行A / D转换，该采样时钟信号具有作为符号时间段的时间段。相位检测器接收从A / D转换器采样的连续的第一和第三数据，通过加上第一和第三数据来计算第二数据，确定由第一和第三数据形成的信号转换是否在预定的并且将第二数据的极性与第一和第三数据之一的极性进行比较，并且当信号转变越过零值时，生成比较结果作为相位检测信号。环路滤波器通过相位检测信号的低频分量。压控振荡器根据环路滤波器的输出信号将采样时钟信号提供给A / D转换器。

3. 发明授权

US08675771B2 Log likelihood ratio arithmetic circuit, transmission apparatus, log likelihood ratio arithmetic method, and program 有权
标题翻译：对数似然比运算电路，传输装置，对数似然比算术方法和程序
公开(公告)号：US08675771B2
公开(公告)日：2014-03-18
申请号：US12083234
申请日：2006-09-29
申请人： Eisaku Sasaki
发明人： Eisaku Sasaki
IPC分类号： H04L27/36
CPC分类号： H04L25/067 , H04L27/38
摘要： A log likelihood ratio arithmetic circuit for calculating a log likelihood ratio from information of a coordinate of a reception signal point to be applied to a communication system using a quadrature amplitude modulation method, wherein the circuit limits a scope within which a value of the log likelihood ratio varies corresponding to a position of the reception signal point to a range between adjacent signal points including a hard-decision threshold of a bit, and wherein the value of the log likelihood ratio does not vary outside of the range between the adjacent signal points.
摘要翻译：一种对数似然比运算电路，用于使用正交幅度调制方法从应用于通信系统的接收信号点的坐标的信息计算对数似然比，其中电路限制对数似然比值比例对应于接收信号点的位置变化到包括比特的硬判决阈值的相邻信号点之间的范围，并且其中对数似然比的值不在相邻信号点之间的范围之外变化。

4. 发明授权

US08527847B2 Channel switching signal generating circuit and channel switching signal generating method 有权
标题翻译：信道切换信号发生电路和信道切换信号生成方法
公开(公告)号：US08527847B2
公开(公告)日：2013-09-03
申请号：US12441243
申请日：2007-09-21
申请人： Eisaku Sasaki
发明人： Eisaku Sasaki
IPC分类号： H03M13/00
CPC分类号： B23B5/166 , H03M13/1128 , H03M13/2975 , H03M13/353 , H03M13/6337 , Y10T29/49748 , Y10T29/51 , Y10T409/304256
摘要： An error correction decoder (101) counts the number of times of iterative decoding executed in the process of a predetermined error correcting operation, and outputs the iterative decoding count to an averaging circuit (102). The averaging circuit (102) calculates the average value of the iterative decoding counts input from the error correction decoder (101), and outputs the calculated average value of the iterative decoding counts to a comparator (103). The comparator (103) determines whether the iterative decoding count average value is larger than a predetermined threshold value. When determining that the average value is larger than the predetermined threshold value, the comparator (103) determines that a channel switching condition is met, and outputs a channel switching signal to a channel switching circuit (405). This makes it possible to output the channel switching signal under appropriate conditions without increasing the number of circuits in a wireless communication system using a highly coding gain code to be iteratively decoded.
摘要翻译：纠错解码器（101）对在预定纠错操作的处理中执行的迭代解码的次数进行计数，并将迭代解码计数输出到平均电路（102）。平均电路（102）计算从纠错解码器（101）输入的迭代解码计数的平均值，并将计算出的迭代解码计数的平均值输出到比较器（103）。比较器（103）确定迭代解码计数平均值是否大于预定阈值。当确定平均值大于预定阈值时，比较器（103）确定信道切换条件被满足，并将信道切换信号输出到信道切换电路（405）。这使得可以在适当的条件下输出信道切换信号，而不需要使用要重复解码的高度编码增益码来增加无线通信系统中的电路数量。

5. 发明申请

US20130181770A1 PLL CIRCUIT 审中-公开
标题翻译： PLL电路
公开(公告)号：US20130181770A1
公开(公告)日：2013-07-18
申请号：US13822531
申请日：2011-09-20
申请人： Eisaku Sasaki
发明人： Eisaku Sasaki
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/091 , H04L27/0014 , H04L27/38 , H04L2027/0067
摘要： A PLL circuit, for extracting phase error information from a demodulated signal in which a variance of a phase or an amplitude changes depending on a signal-to-noise power ratio, and providing negative feedback control, to thereby suppress a phase error of the demodulated signal, includes: a phase error detector for producing a phase error signal corresponding to a value of the phase error as the phase error information; a limiter circuit for limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and a loop filter for producing a control signal based on the limited phase error signal to determine frequency characteristics.
摘要翻译： PLL电路，用于从相位或幅度的方差根据信噪比功率比而变化的解调信号中提取相位误差信息，并提供负反馈控制，从而抑制解调后的相位误差信号包括：相位误差检测器，用于产生与相位误差值相对应的相位误差信号作为相位误差信息; 限制电路，用于将相位误差信号的表达范围限制在一定值以下，以产生有限的相位误差信号; 以及环路滤波器，用于基于有限相位误差信号产生控制信号，以确定频率特性。

6. 发明授权

US06624691B1 Demodulator for processing digital signal 有权
标题翻译：解调器用于处理数字信号
公开(公告)号：US06624691B1
公开(公告)日：2003-09-23
申请号：US09857130
申请日：2001-06-01
申请人： Eisaku Sasaki
发明人： Eisaku Sasaki
IPC分类号： H03D300
CPC分类号： H04L27/22 , H04L27/2273 , H04L2027/0057 , H04L2027/0067 , H04L2027/0069
摘要： The serial data signal obtained by carrying out an N/D conversion at two times the modulation speed is S/P-converted, at a data ratio of 1:2, into a pair of parallel data signals of the modulation speed. The demodulation process is carried out by parallelly processing the pair of parallel data signals, resulting in that the demodulation speed is equal to the modulation speed. The serial data obtained by carrying out the A/D conversion at four times the modulation speed is S/P-converted at a data ratio of 1:4, and is then similarly subjected to demodulation at the demodulation speed equal to the modulation speed. With this arrangement, the demodulator carrying out the digital signal processing can be applied to communication systems having a high modulation speed.
摘要翻译：通过以调制速度的两倍进行N / D转换而获得的串行数据信号以1：2的数据比率被S / P转换为调制速度的一对并行数据信号。通过并行处理该对并行数据信号来进行解调处理，导致解调速度等于调制速度。通过以调制速度的四倍进行A / D转换而获得的串行数据以1：4的数据比进行S / P转换，然后类似地以等于调制速度的解调速度进行解调。利用这种布置，执行数字信号处理的解调器可以应用于具有高调制速度的通信系统。

7. 发明授权

US5031133A FIR digital filter for high-speed communications systems 失效
标题翻译： FIR数字滤波器用于高速通信系统
公开(公告)号：US5031133A
公开(公告)日：1991-07-09
申请号：US480998
申请日：1990-02-16
申请人： Eisaku Sasaki
发明人： Eisaku Sasaki
IPC分类号： H04L27/00 , H03H17/00 , H03H17/06
CPC分类号： H03H17/06
摘要： A Finite Impulse Response (FIR) filter comprising (2n+1) successive virtual taps having virtual tap weight coefficients c.sub.j, where n.gtoreq.2 and 1.ltoreq.j.ltoreq.2n+1, and c.sub.j =c.sub.2n+2-j. Tap weight multipliers are connected to the input terminal of the filter to form (n+1) successive physical taps and multiply input digital samples a.sub.i with physical tap weight coefficients d.sub.k to produce weighted digital samples, where k is a variable in the range between 1 and n+1, and d.sub.k =c.sub.2k-1 +c.sub.2k =c.sub.2(n-k+1) +C.sub.2(n-k+1), and d.sub.n+1 =c.sub.1 =c.sub.2n+1. First shift registers with delay time T and first adders are alternately series-connected from the output of a first one of the multipliers so that the outputs of the other multipliers are summed with successive outputs of the first shift registers to produce a first output sequence. Second shift registers with delay time T and second adders are alternately series-connected from the output of a last one of the multipliers so that the outputs of the other tap weight multipliers are summed with successive outputs of said second shift register to produce a second output sequence. The first output sequence is sampled at intervals T for a first half duration the second output sequence is sampled at intervals T for a second half duration and multiplexed with the sampled first output sequence into a sequence of output digital samples for coupling to the output terminal of the filter.

8. 发明授权

US4864244A Stepped square-QAM demodulator utilizing all signal points to generate control signals 失效
标题翻译：使用所有信号点的步进平方QAM解调器来产生控制信号
公开(公告)号：US4864244A
公开(公告)日：1989-09-05
申请号：US246863
申请日：1988-09-20
申请人： Eisaku Sasaki
发明人： Eisaku Sasaki
IPC分类号： H04L27/38
CPC分类号： H04L27/38
摘要： In a stepped square QAM demodulator, each of the I- and Q-channel demodulated analog signals is supplied to an AGC and/or dc offset controller and converted to an N-bit digital signal by comparison with prescribed decision thresholds. The digital signals of outermost signal points in the stepped square phasor diagram of the SS-QAM system are converted to digital signals of signal points which form corner portions of a true square phasor diagram and the digital signals of inner signal points of the stepped square phasor diagram are converted to digital signals of corresponding signal points in the true square phasor diagram. An M-bit main data signal is derived from all of the converted digital signals (where M is smaller than N) and an auxiliary data signal is generated representing whether the M-bit main data signal represents the digital signals of the inner or outermost signal points. A first error signal representative of an error component of the M-bit main data signal and a second error signal representative of an error component of the auxiliary data signal are generated and selectively applied to a control signal generator in response to the auxiliary data signal together with the main data signal to generate a control signal for application to the AGC and/or dc offset controller.

9. 发明授权

US08229022B2 Modulation and demodulation method, modulation apparatus and demodulation apparatus 有权
标题翻译：调制解调方法，调制装置和解调装置
公开(公告)号：US08229022B2
公开(公告)日：2012-07-24
申请号：US12090126
申请日：2006-10-20
申请人： Seiichi Noda , Eisaku Sasaki
发明人： Seiichi Noda , Eisaku Sasaki
IPC分类号： H04L25/49
CPC分类号： H04L27/3405 , H04L25/067 , H04L27/3488
摘要： The present invention relates to a modulation and demodulation method of minimizing an error rate and applying it to a differential operation modulo 4. A modulation apparatus includes a Gray coding circuit 101 to which data of (2n+1) bits are inputted (where “n” is an integer more than 1) and which encodes 2 bits of an input signal of (2n+1) bits to a Gray code as a signal for allowing four quadrants to be identified, an encoding circuit 102 that encodes 3 bits of the input signal of (2n+1) bits as a signal indicating any one of eight subgroups provided in each of the four quadrants so that an average Hamming distance between adjacent subgroups within its quadrant becomes a minimum, and a mapping circuit 104 that maps binary data encoded by the Gray coding circuit 101 and the encoding circuit 102 on the four quadrants.
摘要翻译：本发明涉及一种使误码率最小化并将其应用于模4的差分运算的调制和解调方法。调制装置包括：格雷编码电路101，输入（2n + 1）比特的数据（其中“n” “是大于1的整数”，并将2比特的（2n + 1）位的输入信号编码为格雷码作为用于允许识别四个象限的信号;编码电路102，其编码3比特的输入（2n + 1）位的信号作为指示在四个象限中的每一个中提供的八个子组中的任何一个的信号，使得其象限内的相邻子组之间的平均汉明距离变为最小值，并且映射电路104将二进制数据编码由格雷编码电路101和编码电路102在四个象限上。

10. 发明申请

US20090292967A1 CHANNEL SWITCHING SIGNAL GENERATING CIRCUIT AND CHANNEL SWITCHING SIGNAL GENERATING METHOD 有权
标题翻译：信道切换信号生成电路和信道切换信号生成方法
公开(公告)号：US20090292967A1
公开(公告)日：2009-11-26
申请号：US12441243
申请日：2007-09-21
申请人： Eisaku Sasaki
发明人： Eisaku Sasaki
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： B23B5/166 , H03M13/1128 , H03M13/2975 , H03M13/353 , H03M13/6337 , Y10T29/49748 , Y10T29/51 , Y10T409/304256
摘要： An error correction decoder (101) counts the number of times of iterative decoding executed in the process of a predetermined error correcting operation, and outputs the iterative decoding count to an averaging circuit (102). The averaging circuit (102) calculates the average value of the iterative decoding counts input from the error correction decoder (101), and outputs the calculated average value of the iterative decoding counts to a comparator (103). The comparator (103) determines whether the iterative decoding count average value is larger than a predetermined threshold value. When determining that the average value is larger than the predetermined threshold value, the comparator (103) determines that a channel switching condition is met, and outputs a channel switching signal to a channel switching circuit (405). This makes it possible to output the channel switching signal under appropriate conditions without increasing the number of circuits in a wireless communication system using a highly coding gain code to be iteratively decoded.
摘要翻译：纠错解码器（101）对在预定纠错操作的处理中执行的迭代解码的次数进行计数，并将迭代解码计数输出到平均电路（102）。平均电路（102）计算从纠错解码器（101）输入的迭代解码计数的平均值，并将计算出的迭代解码计数的平均值输出到比较器（103）。比较器（103）确定迭代解码计数平均值是否大于预定阈值。当确定平均值大于预定阈值时，比较器（103）确定信道切换条件被满足，并将信道切换信号输出到信道切换电路（405）。这使得可以在适当的条件下输出信道切换信号，而不需要使用要重复解码的高度编码增益码来增加无线通信系统中的电路数量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式