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1. 发明申请

US20050114804A1 Method and apparatus for finding optimal unification substitution for formulas in technology library 有权
公开(公告)号：US20050114804A1
公开(公告)日：2005-05-26
申请号：US10719787
申请日：2003-11-21
申请人： Elyar Gasanov , Alexander Podkolzin , Alexei Galatenko
发明人： Elyar Gasanov , Alexander Podkolzin , Alexei Galatenko
IPC分类号： G06F17/10 , G06F17/50
CPC分类号： G06F17/505
摘要： The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a method for finding an optimal unification substitution for formulas in a technology library during integrated circuit design may include the following steps: (a) receiving input including a list L of pairs of formulas in standard form, a set S of substitutions for variables, a right part e(x1, . . . , xp) of an identity, and an information I={t, h, r, a, p} on best application; (b) when the list L is not empty, extracting and removing first pair (f′(A′1, . . . , A′n′), g′(B′1, . . . , B′m′)) from the list L; (c) removing head inverters and buffers from formulas f′(A′1, . . . , A′n′) and g′(B′1, . . . , B′m′)) and obtaining a pair (f(A1, . . . , An), g(B1, . . . , Bm)); (d) when the ƒ is a commutative operation but neither a variable nor constant, and when heads of the formulas f(A1, . . . , An) and g(B1, . . . , Bm) are equal, searching for a basic argument Aj of the formula f(A1, . . . , An); (e) when the basic argument Aj is found, letting P be head of said Aj and setting i=1; (f) when head of Bi is equal to the P, making copy L′ of the list L and making copy S′ of the set S; and (g) forming a reduced pair (A′, B′) for pairs (f(A1, . . . , An), f(B1, . . . , Bn)) and (Aj, Bi) and adding the pairs (Aj, Bi) and (A′, B′) to the list L′.

2. 发明申请

US20070050744A1 METHOD OF SELECTING CELLS IN LOGIC RESTRUCTURING 失效
标题翻译：在逻辑重构中选择细胞的方法
公开(公告)号：US20070050744A1
公开(公告)日：2007-03-01
申请号：US11551573
申请日：2006-10-20
申请人： Iliya Lyalin , Andrej Zolotykh , Elyar Gasanov , Alexei Galatenko
发明人： Iliya Lyalin , Andrej Zolotykh , Elyar Gasanov , Alexei Galatenko
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.
摘要翻译：本公开涉及一种用于选择用于原始设计的逻辑重组的集成电路中的单元的方法。原始设计包括一组参数。该方法包括形成将包括用于逻辑重组的所选择的单元的重构集合和候选集。重组集合包括具有初始单元格的重组单元。重组集合适于接受被称为重组细胞的额外细胞。候选集合适于包括候选小区，其中候选集合中的每个候选小区连接到重组集合中的至少一个重组小区。候选集合适于从候选集中移除候选细胞。如果在参数集合中包括相应的参数，则重组集合适于接受所选择的被移除的候选小区作为已识别的重组小区。

3. 发明申请

US20050210422A1 Method and apparatus for performing logical transformations for global routing 失效
标题翻译：用于执行全局路由的逻辑转换的方法和装置
公开(公告)号：US20050210422A1
公开(公告)日：2005-09-22
申请号：US10803516
申请日：2004-03-17
申请人： Alexei Galatenko , Elyar Gasanov , Andrej Zolotykh
发明人： Alexei Galatenko , Elyar Gasanov , Andrej Zolotykh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077
摘要： The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters. This may be achieved by assigning the same coordinates to nodes of degree !=2 of homeomorphic trees, which means that one may assign the coordinates of corresponding nodes to “essential” nodes and then insert or remove nodes of degree 2.
摘要翻译：本发明提供了一种用于优化全局路由中的各种设计参数的新方法和算法。根据本发明的示例性方面，首先对标记的树进行预处理。对于每个离开的顶点，可以通过它的叶子列表，如果两个叶子有相同的标记，那么可以只留下其中一个。之后，可以确定是否存在同胚。选择这种同胚对之后的原因如下：添加或删除2级顶点以及添加或删除新叶（变量）不会显着修改路由（在这种情况下，所有路由转换本质上都是分割和合并路由树）。选择适用的变换后，可以应用它们来优化设计参数。这可以通过将相同的坐标分配给同胚树的度数= 2的节点来实现，这意味着可以将对应节点的坐标分配给“必需”节点，然后插入或移除度数2的节点。

4. 发明申请

US20070234255A1 RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES 失效
标题翻译：带循环设计的RAMPTIME传播
公开(公告)号：US20070234255A1
公开(公告)日：2007-10-04
申请号：US11757229
申请日：2007-06-01
申请人： Andrej Zolotykh , Elyar Gasanov , Alexei Galatenko , Ilya Lyalin
发明人： Andrej Zolotykh , Elyar Gasanov , Alexei Galatenko , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.
摘要翻译：描述了一种用于计算具有在一个或多个闭环中的定向图中互连的引脚的集成电路布图图案的突触传播的方法和装置。对于第一组引脚计算Ramptime值，它们不连接到闭环，同时留下第二组引脚具有未知的ramptime值。一个或多个闭环通过从第二组中的引脚回溯具有未知的ramptime值来识别。迭代地计算一个或多个闭环中每个引脚的ramptime值。

5. 发明申请

US20060112361A1 Method of selecting cells in logic restructuring 有权
公开(公告)号：US20060112361A1
公开(公告)日：2006-05-25
申请号：US10992941
申请日：2004-11-19
申请人： Iliya Lyalin , Andrej Zolotykh , Elyar Gasanov , Alexei Galatenko
发明人： Iliya Lyalin , Andrej Zolotykh , Elyar Gasanov , Alexei Galatenko
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505
摘要： The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

6. 发明申请

US20070094631A1 Method and apparatus for controlling congestion during integrated circuit design resynthesis 失效
标题翻译：集成电路设计再合成过程中控制拥堵的方法和装置
公开(公告)号：US20070094631A1
公开(公告)日：2007-04-26
申请号：US11258738
申请日：2005-10-26
申请人： Alexei Galatenko , Elyar Gasanov , Iliya Lyalin
发明人： Alexei Galatenko , Elyar Gasanov , Iliya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/84
摘要： The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.
摘要翻译：本公开涉及一种用于将集成电路设计字段划分为具有用户可选择尺寸的多个拥塞矩形的方法和装置。在设计字段内路由互连之前，为每个拥塞矩形估计路由拥塞值。拥塞值存储在机器可读存储器中，并响应于设计领域内的线路更改而被更新。

7. 发明申请

US20060123369A1 Ramptime propagation on designs with cycles 有权
标题翻译：在具有周期的设计上的Ramptime传播
公开(公告)号：US20060123369A1
公开(公告)日：2006-06-08
申请号：US11004309
申请日：2004-12-03
申请人： Andrej Zolotykh , Elyar Gasanov , Alexei Galatenko , Ilya Lyalin
发明人： Andrej Zolotykh , Elyar Gasanov , Alexei Galatenko , Ilya Lyalin
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.
摘要翻译：描述了一种用于计算具有在一个或多个闭合回路中的定向图中互连的引脚的集成电路布图图案的突发时间传播的方法。对于第一组引脚计算Ramptime值，它们不连接到闭环，同时留下第二组引脚具有未知的ramptime值。一个或多个闭环通过从第二组中的引脚回溯具有未知的ramptime值来识别。迭代地计算一个或多个闭环中每个引脚的ramptime值。

8. 发明申请

US20060112363A1 Multiple buffer insertion in global routing 有权
标题翻译：在全局路由中插入多个缓冲区
公开(公告)号：US20060112363A1
公开(公告)日：2006-05-25
申请号：US10992999
申请日：2004-11-19
申请人： Alexei Galatenko , Elyar Gasanov , Andrej Zolotykh , Ilya Lyalin
发明人： Alexei Galatenko , Elyar Gasanov , Andrej Zolotykh , Ilya Lyalin
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.
摘要翻译：使用基于缓冲器高度，输入电容，输出电容和延迟时间来识别缓冲器类型的表，将缓冲器插入到集成电路芯片设计中。创建具有根，内部和叶子顶点的缓冲区路由树。对于每个内部顶点，将初始电路参数与与表中标识的缓冲器相关联的电路参数进行比较，以识别表中识别的缓冲区是否可以插入到相应的内部顶点。如果可以，则至少部分地基于比较结果，从表中选择最佳可插入缓冲器并将其插入到选定的内部顶点。还描述了创建缓冲器类型表的计算机处理。

9. 发明申请

US20060048087A1 Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths 有权
公开(公告)号：US20060048087A1
公开(公告)日：2006-03-02
申请号：US10928799
申请日：2004-08-27
申请人： Elyar Gasanov , Iliya Lyalin , Alexei Galatenko , Andrej Zolotykh
发明人： Elyar Gasanov , Iliya Lyalin , Alexei Galatenko , Andrej Zolotykh
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.

10. 发明申请

US20050114813A1 Process and apparatus for placement of megacells in ICs design 有权
标题翻译：在IC设计中放置大型电池的工艺和设备
公开(公告)号：US20050114813A1
公开(公告)日：2005-05-26
申请号：US10719393
申请日：2003-11-21
申请人： Alexei Galatenko , Valeriy Kudryavtsev , Elyar Gasanov
发明人： Alexei Galatenko , Valeriy Kudryavtsev , Elyar Gasanov
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An IC layout containing megacells placed in violation of design rules is corrected to remove design rule violations while maintaining the original placement as near as practical. The sizes of at least some of the megacells are inflated. The megacells are placed and moved in a footprint of the circuit in a manner to reduce placement complexity. The placement of the megacells is permuted to reduce placement complexity. Additional movements are be applied to the permuted placement to further reduce placement complexity.
摘要翻译：包含违反设计规则的大型电力设备的IC布局被更正，以消除设计规则违规，同时将原始位置保持在可接近的范围内。至少一些大型电池的尺寸是膨胀的。这些巨型电池以一种降低放置复杂性的方式放置并移动到电路的占位面积中。大容量的放置被置换以减少放置复杂性。额外的运动可应用于排列的位置，以进一步降低放置复杂性。

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