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1. 发明申请

US20090123589A1 METHODS INVOLVING MARKING MOLDS 有权
标题翻译：涉及标记的方法
公开(公告)号：US20090123589A1
公开(公告)日：2009-05-14
申请号：US11939604
申请日：2007-11-14
申请人： Eric Bouchard , Luc Guerin , Robert G. Haas
发明人： Eric Bouchard , Luc Guerin , Robert G. Haas
IPC分类号： B28B17/00
CPC分类号： C03C19/00 , Y10T409/303808
摘要： An exemplary method for marking molds, the method comprising, configuring a milling machine to operate with a diamond coated bit having an angle of approximately 60 degrees, and engraving a unique identifier on a bottom surface of a borosilicate glass injection molded soldering mold with the milling machine.
摘要翻译：一种用于标记模具的示例性方法，所述方法包括：将铣床配置成与具有约60度角度的金刚石涂层钻头一起操作，以及在硼硅酸盐玻璃注射成型焊接模具的底表面上雕刻独特的标识符，其中铣削机。

2. 发明授权

US07837419B2 Methods involving marking molds 有权
标题翻译：包括标记模具的方法
公开(公告)号：US07837419B2
公开(公告)日：2010-11-23
申请号：US11939604
申请日：2007-11-14
申请人： Eric Bouchard , Luc Guerin , Robert G Haas
发明人： Eric Bouchard , Luc Guerin , Robert G Haas
IPC分类号： B23C3/00 , B43L13/00
CPC分类号： C03C19/00 , Y10T409/303808
摘要： An exemplary method for marking molds, the method comprising, configuring a milling machine to operate with a diamond coated bit having an angle of approximately 60 degrees, and engraving a unique identifier on a bottom surface of a borosilicate glass injection molded soldering mold with the milling machine.
摘要翻译：一种用于标记模具的示例性方法，所述方法包括：将铣床配置成与具有约60度角度的金刚石涂层钻头一起操作，以及在硼硅酸盐玻璃注射成型焊接模具的底表面上雕刻独特的标识符，其中铣削机。

3. 发明授权

US08383505B2 Solder ball contact susceptible to lower stress 有权
标题翻译：焊球接触容易受到较低的应力
公开(公告)号：US08383505B2
公开(公告)日：2013-02-26
申请号：US13080105
申请日：2011-04-05
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L21/00
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.
摘要翻译：焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

4. 发明申请

US20110044369A1 SILICON CARRIER OPTOELECTRONIC PACKAGING 有权
标题翻译：硅载体光电包装
公开(公告)号：US20110044369A1
公开(公告)日：2011-02-24
申请号：US12544696
申请日：2009-08-20
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
IPC分类号： H01S5/18 , H01L31/0232 , H01L23/34 , H01L21/50
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

5. 发明申请

US20070007323A1 STANDOFF STRUCTURES FOR SURFACE MOUNT COMPONENTS 审中-公开
标题翻译：表面安装组件的标准结构
公开(公告)号：US20070007323A1
公开(公告)日：2007-01-11
申请号：US11160702
申请日：2005-07-06
申请人： David Russell , Luc Guerin , Mario Interrante , Steven Ostrander , Anna Spencer , Van Truong
发明人： David Russell , Luc Guerin , Mario Interrante , Steven Ostrander , Anna Spencer , Van Truong
IPC分类号： B23K31/02 , B23K35/12
CPC分类号： B23K1/0016 , B23K2101/40 , H05K3/303 , H05K3/3452 , H05K2201/09909 , H05K2201/10636 , H05K2201/2036 , H05K2203/0588 , Y02P70/611 , Y02P70/613
摘要： Increasing standoff height for surface mount components mounted to a laminate by image screening at least one standoff structure in a footprint area on the laminate surface. The standoff structure may comprise a filled epoxy and curing agents and may be cured by thermal treatment or by exposure to actinic radiation. The use of legend ink as a standoff structure offers a method and a structure for improving component standoff height without additional processing operations or cost.
摘要翻译：通过图像筛选层压板表面上的覆盖区域中的至少一个间隔结构来增加安装到层压板上的表面贴装部件的间隔高度。间隔结构可以包括填充的环氧树脂和固化剂，并且可以通过热处理或通过暴露于光化辐射来固化。使用传说油墨作为隔离结构提供了一种用于提高部件间隔高度的方法和结构，而没有附加的处理操作或成本。

6. 发明授权

US07066740B2 Area array package with low inductance connecting device 失效
标题翻译：具有低电感连接装置的面阵阵列封装
公开(公告)号：US07066740B2
公开(公告)日：2006-06-27
申请号：US10604555
申请日：2003-07-30
申请人： Jean Audet , Luc Guerin , Jean-Luc Landreville , Gerald Pieree Audet
发明人： Jean Audet , Luc Guerin , Jean-Luc Landreville , Gerald Pieree Audet
IPC分类号： H01R12/00 , H05K1/00
CPC分类号： H01R12/57 , H01L23/49811 , H01L2224/16 , H01L2224/16235 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/16152 , H01L2924/3011 , H01L2924/3025 , H01R12/718 , H05K3/3426 , Y02P70/613
摘要： An area-array integrated circuit package assembly are provided with a plurality of electrically conductive connectors attached to the package I.O. pads, that are used to connect the package to a printed circuit card or other component. The connectors comprise at least two parallel conductors flexing together in the same direction, electrically insulated from each other for a portion of their length between the package and printed circuit card to provide for reduced interconnection inductance. The connection with the component contact pads can be achieved by mechanically pressing the package and circuit card together or with the use of bonding material.
摘要翻译：区域阵列集成电路封装组件设置有多个连接到封装件I.O的导电连接器。垫，用于将包装连接到印刷电路卡或其他组件。连接器包括至少两个平行的导体，它们沿相同方向弯曲在一起，在封装和印刷电路卡之间的长度的一部分彼此电绝缘以提供减小的互连电感。与元件接触焊盘的连接可以通过将封装和电路卡机械地压在一起或使用粘合材料来实现。

7. 发明授权

US06302702B1 Connecting devices and method for interconnecting circuit components 有权
标题翻译：连接设备和互连电路组件的方法
公开(公告)号：US06302702B1
公开(公告)日：2001-10-16
申请号：US09516904
申请日：2000-03-01
申请人： Gerald P. Audet , Luc Guerin , Jean-Luc Landreville
发明人： Gerald P. Audet , Luc Guerin , Jean-Luc Landreville
IPC分类号： H01R100
CPC分类号： H01R12/57 , H01L23/49811 , H01L2224/16225 , H01L2224/16235 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H05K3/325 , H05K7/1061 , Y10T29/49149
摘要： An integrated circuit package having metallized contact pads is provided with electrically conducting devices permanently attached to each contact pad. The devices are flexed when so attached, and are aligned and assembled onto corresponding pads of a second electrical component (e.g., a printed circuit board) to provide electrical connection between the integrated circuit package and the second electrical component.
摘要翻译：具有金属化接触焊盘的集成电路封装设置有永久地附接到每个接触焊盘的导电装置。当这样安装时，这些装置被弯曲，并被对准并组装到第二电气部件（例如，印刷电路板）的相应焊盘上，以提供集成电路封装和第二电气部件之间的电连接。

8. 发明申请

US20120326290A1 SILICON CARRIER OPTOELECTRONIC PACKAGING 有权
标题翻译：硅载体光电包装
公开(公告)号：US20120326290A1
公开(公告)日：2012-12-27
申请号：US13604341
申请日：2012-09-05
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chrirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chrirag S. Patel
IPC分类号： H01L23/34 , H01L21/50
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

9. 发明申请

US20120300220A1 TECHNIQUE FOR VERIFYING THE MICROSTRUCTURE OF LEAD-FREE INTERCONNECTS IN SEMICONDUCTOR ASSEMBLIES 有权
标题翻译：用于验证半导体组件中无铅互连的微结构的技术
公开(公告)号：US20120300220A1
公开(公告)日：2012-11-29
申请号：US13115823
申请日：2011-05-25
申请人： Christian Bergeron , Pascal Blais , Clement Fortin , Luc Guerin
发明人： Christian Bergeron , Pascal Blais , Clement Fortin , Luc Guerin
IPC分类号： G01B11/24
CPC分类号： G01B11/24 , G01B2210/56
摘要： A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.
摘要翻译：用于验证倒装芯片应用中的互连的内部微结构的方法包括提供包括以下的微电子组件：承载倒装芯片附接焊盘和一个或多个工艺控制焊盘阵列的衬底; 具有与倒装芯片附接焊盘阵列接触的焊料凸块阵列的倒装芯片; 以及一个或多个代表性的焊料凸块与一个或多个工艺控制焊盘接触。代表性的焊料凸块具有与焊料凸块阵列基本相似或相同的化学组成。然后将回流循环施加到微电子组件以熔化并固化倒装芯片附接焊盘上的焊料凸块阵列，并熔化并固化过程控制焊盘上的代表性焊料凸块。然后对代表性焊料凸块的表面纹理进行光学检查，以确定焊料凸块阵列的内部微结构。

10. 发明申请

US20120256313A1 SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS 有权
标题翻译：焊球接触不牢固到下压
公开(公告)号：US20120256313A1
公开(公告)日：2012-10-11
申请号：US13080105
申请日：2011-04-05
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L23/498 , H01L21/28
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.
摘要翻译：焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

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