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1. 发明申请

US20090257451A1 Method and apparatus to align and standardize packet based parallel interfaces 有权
标题翻译：调整和标准化基于数据包的并行接口的方法和装置
公开(公告)号：US20090257451A1
公开(公告)日：2009-10-15
申请号：US12082380
申请日：2008-04-10
申请人： Eugene Saghi , Richard L. Solomon , Robert E. Ward
发明人： Eugene Saghi , Richard L. Solomon , Robert E. Ward
IPC分类号： H04L29/02
CPC分类号： G06F13/385 , H04L1/0061
摘要： A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.
摘要翻译：用于预处理/对准输入分组的分组对准系统可以包括用于接收控制信号和数据信号的一个或多个寄存器。对准器可循环移位所述数据信号以形成多个移位数据字。多个管道寄存器可以针对多个移位数据字中的每一个收集并产生经调整的控制信号。滤波逻辑可以将多个移位的数据字中的一个识别为期望对准的数据字。滤波器逻辑还可以被配置用于分别在头部寄存器，有效载荷寄存器和ECRC寄存器中注册包含在期望对准的数据字中的头部数据，有效载荷数据和ECRC数据。输出接口可以产生输出信号并且从头部寄存器，有效载荷寄存器和ECRC寄存器中的至少一个提供数据。

2. 发明授权

US07701977B2 Method and apparatus to align and standardize packet based parallel interfaces 有权
标题翻译：调整和标准化基于数据包的并行接口的方法和装置
公开(公告)号：US07701977B2
公开(公告)日：2010-04-20
申请号：US12082380
申请日：2008-04-10
申请人： Eugene Saghi , Richard L. Solomon , Robert E. Ward
发明人： Eugene Saghi , Richard L. Solomon , Robert E. Ward
IPC分类号： H04J3/00
CPC分类号： G06F13/385 , H04L1/0061
摘要： A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.
摘要翻译：用于预处理/对准输入分组的分组对准系统可以包括用于接收控制信号和数据信号的一个或多个寄存器。对准器可循环移位所述数据信号以形成多个移位数据字。多个管道寄存器可以针对多个移位数据字中的每一个收集并产生经调整的控制信号。滤波逻辑可以将多个移位的数据字中的一个识别为期望对准的数据字。滤波器逻辑还可以被配置用于分别在头部寄存器，有效载荷寄存器和ECRC寄存器中注册包含在期望对准的数据字中的头部数据，有效载荷数据和ECRC数据。输出接口可以产生输出信号并且从头部寄存器，有效载荷寄存器和ECRC寄存器中的至少一个提供数据。

3. 发明授权

US07237043B2 System for improving PCI write performance 有权
标题翻译：提高PCI写入性能的系统
公开(公告)号：US07237043B2
公开(公告)日：2007-06-26
申请号：US10718937
申请日：2003-11-21
申请人： Richard L. Solomon , Eugene Saghi , Amanda White
发明人： Richard L. Solomon , Eugene Saghi , Amanda White
IPC分类号： G06F3/00 , G06F9/26 , G06F13/00 , G06F5/00
CPC分类号： G06F13/423
摘要： A method and apparatus for traversing a queue of commands containing a mixture of read and write commands places a Next Valid Write Address pointer in each queue entry. In this manner, time savings are achieved by allowing preprocessing of the next write command to be executed. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.
摘要翻译：用于遍历包含读取和写入命令的混合的命令队列的方法和装置在每个队列条目中放置下一个有效写入地址指针。以这种方式，通过允许执行下一个写入命令的预处理来实现时间节省。该方法可以通过在所有队列条目中设置下一个有效的地址指针来实现。队列遍历可以是前向，后向或双向。

4. 发明授权

US06968409B1 Method and apparatus of establishing a dynamically adjustable loop of delayed read commands for completion in a queue buffer 失效
标题翻译：在队列缓冲区中建立延迟读取命令的动态可调循环的方法和装置，用于完成
公开(公告)号：US06968409B1
公开(公告)日：2005-11-22
申请号：US09942390
申请日：2001-08-29
申请人： Richard L. Solomon , Eugene Saghi
发明人： Richard L. Solomon , Eugene Saghi
IPC分类号： G06F13/00 , G06F13/38
CPC分类号： G06F13/385
摘要： A loop of delayed read commands is established from a larger set of queued commands. Upon recognizing a delay in completing a first read command which is followed by a second read command, the loop is established by setting loop start pointer to identify the first delayed read command and setting a loop end pointer to identify the second read command. Upon recognizing a delay in completing the second read command which is followed by a third read command, the loop end pointer is advanced to identify the third read command. All of the read commands in the loop at and between the loop start pointer and the loop end pointer are completed before attempting to complete other commands in the queue not within the loop.
摘要翻译：从更大的排队命令集建立延迟读命令循环。在识别出完成第一读取命令的延迟，其后面是第二读取命令时，通过设置循环开始指针来建立循环以识别第一延迟读取命令并设置循环结束指针以识别第二读取命令。当识别到完成第二读取命令的延迟，其后面是第三读取命令时，循环结束指针被提前以识别第三读取命令。在循环开始指针和循环结束指针之间的循环中的所有读取命令都将在尝试完成队列中不在循环内的其他命令之前完成。

5. 发明授权

US08738979B2 Methods and structure for correlation of test signals routed using different signaling pathways 有权
标题翻译：使用不同信号通路路由的测试信号相关性的方法和结构
公开(公告)号：US08738979B2
公开(公告)日：2014-05-27
申请号：US13434962
申请日：2012-03-30
申请人： Paul J. Smith , Jeffrey K. Whitt , Eugene Saghi , Douglas J. Saxon , Joshua P. Sinykin
发明人： Paul J. Smith , Jeffrey K. Whitt , Eugene Saghi , Douglas J. Saxon , Joshua P. Sinykin
IPC分类号： G01R31/28 , G01R31/319 , G01R31/317
CPC分类号： G01R31/31922 , G01R31/31707 , G01R31/31723 , G01R31/31727 , G01R31/31915
摘要： Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.
摘要翻译：将通过测试信号选择层次的不同路径路由的内部操作信号相关联的方法和结构。该结构包括可操作以产生内部操作信号和时钟信号的电路的功能块。集成电路还包括可操作以接收内部操作信号和时钟信号并且选择性地路由内部操作信号和时钟信号的测试信号选择层级。此外，结构包括控制单元，其可操作以从测试信号选择层级接收时钟信号，以确定通过测试信号选择层级的不同信令路径路由的接收时钟信号之间的延迟。控制单元进一步可操作地基于时钟信号之间的延迟并基于与时钟信号相关的内部操作信号对延迟线进行编程。

6. 发明申请

US20130262945A1 METHODS AND STRUCTURE FOR CORRELATING MULTIPLE TEST OUTPUTS OF AN INTEGRATED CIRCUIT ACQUIRED DURING SEPARATE INSTANCES OF AN EVENT 有权
标题翻译：在事件的独立事件中获取的集成电路的多个测试输出的方法和结构
公开(公告)号：US20130262945A1
公开(公告)日：2013-10-03
申请号：US13434940
申请日：2012-03-30
申请人： Eugene Saghi , Jeffrey K. Whitt , Joshua P. Sinykin
发明人： Eugene Saghi , Jeffrey K. Whitt , Joshua P. Sinykin
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31705 , G01R31/31707
摘要： Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.
摘要翻译：提供了对多组测试输出信号进行时间相关的方法和结构。该结构包括集成电路，其包括产生内部操作信号的电路块。电路还包括测试多路复用器（MUX）层级，其选择内部信号的子集并将子集应用于测试元件。时钟发生器产生所选信号的时钟信号。测试逻辑定时器接收时钟信号并增加计数器值，并将计数器值应用于测试元件。事件检测器在检测到事件时重置计数器值，使得响应于对事件的第一实例的检测而获得的从测试MUX层次结构获取的内部信号的第一子集可以与时间上的第二子集相关联响应于事件的第二实例的检测而获取的内部信号。

7. 发明授权

US08108574B2 Apparatus and methods for translation of data formats between multiple interface types 失效
标题翻译：用于在多种接口类型之间翻译数据格式的装置和方法
公开(公告)号：US08108574B2
公开(公告)日：2012-01-31
申请号：US12247769
申请日：2008-10-08
申请人： John C. Udell , Richard Solomon , Eugene Saghi , Jeffrey K. Whitt
发明人： John C. Udell , Richard Solomon , Eugene Saghi , Jeffrey K. Whitt
IPC分类号： G06F13/00 , G06F11/00
CPC分类号： G06F13/4221
摘要： Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit.
摘要翻译：用于在多种接口类型之间翻译数据格式的装置和方法。翻译逻辑插在生成器电路和消费电路之间，以将由生产者生成的数据信号的数据格式转换为消费者。翻译逻辑可以包括多个翻译器，以提供多种生产者数据格式和多种消费者数据格式中的任何一种之间的翻译。因此，一个或多个生成器电路可以通过翻译逻辑电路与一个或多个消费者电路选择性地耦合。

8. 发明授权

US08077620B2 Methods and apparatuses for processing packets in a credit-based flow control scheme 失效
标题翻译：在基于信用的流量控制方案中处理数据包的方法和装置
公开(公告)号：US08077620B2
公开(公告)日：2011-12-13
申请号：US12247845
申请日：2008-10-08
申请人： Richard Solomon , Eugene Saghi
发明人： Richard Solomon , Eugene Saghi
IPC分类号： H04J3/14
CPC分类号： H04L47/39 , H04L47/10 , H04L47/32
摘要： Methods and systems for processing a second request before processing of a first request has completed. The first request is associated with a first flow control credit type, and the second request is associated with a second flow control credit type. After a period of time, the second request is selected for processing based on the first flow control credit type and the second flow control credit type.
摘要翻译：处理第一个请求之前处理第二个请求的方法和系统已经完成。第一请求与第一流控信用类型相关联，第二请求与第二流控信用类型相关联。在一段时间之后，基于第一流量控制信用类型和第二流量控制信用类型选择第二请求进行处理。

9. 发明授权

US08832499B2 Methods and structure for trapping requests directed to hardware registers of an electronic circuit 有权
标题翻译：用于捕获针对电子电路的硬件寄存器的请求的方法和结构
公开(公告)号：US08832499B2
公开(公告)日：2014-09-09
申请号：US13567712
申请日：2012-08-06
申请人： Eugene Saghi , Richard Solomon
发明人： Eugene Saghi , Richard Solomon
IPC分类号： G06F11/00
CPC分类号： G06F9/4411 , G06F9/30101
摘要： Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further operable to access a value in shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.
摘要翻译：提供方法和结构用于捕获针对电子设备的硬件寄存器的传入请求。包括定义电子设备的配置的一组硬件寄存器的电子设备，实现可定义哪些硬件寄存器被标记以捕获传入请求的可编程逻辑的电路，以及包括与标记的硬件寄存器对应的值的影子存储器。电路还可操作以响应于从外部设备接收到访问标记的硬件寄存器的请求来访问对应于标记的硬件寄存器的影子存储器中的值。

10. 发明申请

US20130257512A1 METHODS AND STRUCTURE FOR UTILIZING EXTERNAL INTERFACES USED DURING NORMAL OPERATION OF A CIRCUIT TO OUTPUT TEST SIGNALS 有权
标题翻译：在电路正常运行时使用外部接口的输出测试信号的方法和结构
公开(公告)号：US20130257512A1
公开(公告)日：2013-10-03
申请号：US13434954
申请日：2012-03-30
申请人： Eugene Saghi , Paul J. Smith , Joshua P. Sinykin , Jeffrey K. Whitt
发明人： Eugene Saghi , Paul J. Smith , Joshua P. Sinykin , Jeffrey K. Whitt
IPC分类号： H03K17/00
CPC分类号： G01R31/00 , G01R31/3172
摘要： Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit. The control unit receives the selected internal operational signals from the test signal routing hierarchy, and applies the selected internal operational signals to the external interface during normal operation of the integrated circuit.
摘要翻译：提供了用于路由电路的内部操作信号以经由外部接口输出的方法和结构。该结构包括集成电路。集成电路包括一组电路组件，可操作以产生用于在电路的正常操作期间执行指定功能的内部操作信号，控制单元，测试信号路由层次以及外部接口。耦合测试信号路由层级以接收内部操作信号并可控地选择用于采集的内部操作信号并将其应用于控制单元。外部接口在集成电路的正常操作期间提供集成电路与外部设备之间的通信。控制单元从测试信号路由层次接收所选择的内部操作信号，并且在集成电路的正常操作期间将所选择的内部操作信号施加到外部接口。

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