会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • Method and apparatus to align and standardize packet based parallel interfaces
    • 调整和标准化基于数据包的并行接口的方法和装置
    • US20090257451A1
    • 2009-10-15
    • US12082380
    • 2008-04-10
    • Eugene SaghiRichard L. SolomonRobert E. Ward
    • Eugene SaghiRichard L. SolomonRobert E. Ward
    • H04L29/02
    • G06F13/385H04L1/0061
    • A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.
    • 用于预处理/对准输入分组的分组对准系统可以包括用于接收控制信号和数据信号的一个或多个寄存器。 对准器可循环移位所述数据信号以形成多个移位数据字。 多个管道寄存器可以针对多个移位数据字中的每一个收集并产生经调整的控制信号。 滤波逻辑可以将多个移位的数据字中的一个识别为期望对准的数据字。 滤波器逻辑还可以被配置用于分别在头部寄存器,有效载荷寄存器和ECRC寄存器中注册包含在期望对准的数据字中的头部数据,有效载荷数据和ECRC数据。 输出接口可以产生输出信号并且从头部寄存器,有效载荷寄存器和ECRC寄存器中的至少一个提供数据。
    • 2. 发明授权
    • Method and apparatus to align and standardize packet based parallel interfaces
    • 调整和标准化基于数据包的并行接口的方法和装置
    • US07701977B2
    • 2010-04-20
    • US12082380
    • 2008-04-10
    • Eugene SaghiRichard L. SolomonRobert E. Ward
    • Eugene SaghiRichard L. SolomonRobert E. Ward
    • H04J3/00
    • G06F13/385H04L1/0061
    • A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.
    • 用于预处理/对准输入分组的分组对准系统可以包括用于接收控制信号和数据信号的一个或多个寄存器。 对准器可循环移位所述数据信号以形成多个移位数据字。 多个管道寄存器可以针对多个移位数据字中的每一个收集并产生经调整的控制信号。 滤波逻辑可以将多个移位的数据字中的一个识别为期望对准的数据字。 滤波器逻辑还可以被配置用于分别在头部寄存器,有效载荷寄存器和ECRC寄存器中注册包含在期望对准的数据字中的头部数据,有效载荷数据和ECRC数据。 输出接口可以产生输出信号并且从头部寄存器,有效载荷寄存器和ECRC寄存器中的至少一个提供数据。
    • 4. 发明授权
    • Method and apparatus of establishing a dynamically adjustable loop of delayed read commands for completion in a queue buffer
    • 在队列缓冲区中建立延迟读取命令的动态可调循环的方法和装置,用于完成
    • US06968409B1
    • 2005-11-22
    • US09942390
    • 2001-08-29
    • Richard L. SolomonEugene Saghi
    • Richard L. SolomonEugene Saghi
    • G06F13/00G06F13/38
    • G06F13/385
    • A loop of delayed read commands is established from a larger set of queued commands. Upon recognizing a delay in completing a first read command which is followed by a second read command, the loop is established by setting loop start pointer to identify the first delayed read command and setting a loop end pointer to identify the second read command. Upon recognizing a delay in completing the second read command which is followed by a third read command, the loop end pointer is advanced to identify the third read command. All of the read commands in the loop at and between the loop start pointer and the loop end pointer are completed before attempting to complete other commands in the queue not within the loop.
    • 从更大的排队命令集建立延迟读命令循环。 在识别出完成第一读取命令的延迟,其后面是第二读取命令时,通过设置循环开始指针来建立循环以识别第一延迟读取命令并设置循环结束指针以识别第二读取命令。 当识别到完成第二读取命令的延迟,其后面是第三读取命令时,循环结束指针被提前以识别第三读取命令。 在循环开始指针和循环结束指针之间的循环中的所有读取命令都将在尝试完成队列中不在循环内的其他命令之前完成。
    • 5. 发明授权
    • Method for pre-emptive arbitration
    • 先发制人的仲裁方法
    • US07007122B2
    • 2006-02-28
    • US10306237
    • 2002-11-27
    • Richard L. SolomonRobert E. Ward
    • Richard L. SolomonRobert E. Ward
    • G06F12/00G06F13/14G06F13/38
    • G06F13/4031
    • An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent for access to the interface. A pre-emptive arbiter provides arbitration between the first agent and the second agent when at least one of a first transfer request signal is asserted by the first agent for requesting access to the interface by the first agent and a second transfer request signal is asserted by the second agent for requesting access to the interface by the second agent. The pre-emptive arbiter is capable of synthesizing a transfer completion signal on the interface for preempting access of the first agent to the interface so that access may be granted to the second agent.
    • 能够在多个代理之间提供优先仲裁的接口系统包括包括共享用于传送数据的接口的至少第一代理和第二代理的接口,所述第二代理优先于所述第一代理以访问所述接口。 当第一代理确认第一传输请求信号的第一传送请求信号中的至少一个请求由第一代理接入该接口时,优先仲裁器提供第一代理和第二代理之间的仲裁,并且第二传输请求信号被第一代理断言 用于请求由第二代理访问该接口的第二代理。 优先仲裁器能够在接口上合成传送完成信号,以便抢占第一代理程序访问接口,以便可以向第二代理程序授予访问权限。
    • 8. 发明授权
    • Methods and systems for improving delayed read handling
    • 改进延迟读取处理的方法和系统
    • US07216194B2
    • 2007-05-08
    • US10409569
    • 2003-04-08
    • Richard L. SolomonJill A. Thomas
    • Richard L. SolomonJill A. Thomas
    • G06F13/36
    • G06F13/4027G06F2213/0024
    • Methods and systems for improving delayed read handling in a loop of delayed commands among a larger set of commands in a queue of commands are disclosed. In general, when commands in a delayed loop are completed out of order, “holes” are left in the command queue. Skipping over such “holes” consumes multiple clock cycles before another command can be issued, as each “hole” must be examined first in order to determine that it no longer contains a valid read command. A loop of delayed read commands can thus be created from among a larger set of commands in a queue of commands with each command entry having a pointer to the next valid command. Valid delayed read commands in the loop of commands can then be processed by automatically advancing between any two valid delayed read commands among the loop of commands. In this manner, the time to advance between any two commands in the delayed read loop is constant and PCI read performance thereof can be dramatically improved.
    • 公开了一种用于在命令队列中的较大命令集中的延迟命令循环中延迟读取处理的方法和系统。 一般来说,当延迟循环中的命令按顺序完成时,命令队列中留下“孔”。 跳过这样的“空穴”可以在发出另一个命令之前消耗多个时钟周期,因为必须首先检查每个“孔”,以确定它不再包含有效的读取命令。 因此,可以从命令队列中的更大的一组命令中创建延迟读取命令的循环,其中每个命令条目具有指向下一个有效命令的指针。 命令循环中有效的延迟读取命令可以通过在命令循环中的任意两个有效的延迟读取命令之间自动进行处理。 以这种方式,在延迟读取循环中的任何两个命令之间进行的时间是恒定的,并且可以显着提高其PCI读取性能。