专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180205893A1 SEGMENTED FOCAL PLANE ARRAY ARCHITECTURE 审中-公开
公开(公告)号：US20180205893A1
公开(公告)日：2018-07-19
申请号：US15919116
申请日：2018-03-12
申请人： FLIR SYSTEMS, INC.
发明人： Brian Simolon , Eric A. Kurth , Mark Nussmeier , Nicholas Högasten , Theodore R. Hoelter , Katrin Strandemar , Pierre Boulanger , Barbara Sharp
IPC分类号： H04N5/33 , H01L27/146 , H04N5/225 , H04N5/378
CPC分类号： H04N5/33 , H01L27/14634 , H01L27/1469 , H04N5/2257 , H04N5/378
摘要： Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.

2. 发明申请

US20140108850A1 ABNORMAL CLOCK RATE DETECTION IN IMAGING SENSOR ARRAYS 有权
标题翻译：成像传感器阵列异常时钟频率检测
公开(公告)号：US20140108850A1
公开(公告)日：2014-04-17
申请号：US14106666
申请日：2013-12-13
申请人： FLIR Systems, Inc.
发明人： Brian Simolon , Eric A. Kurth , Jim Goodland , Mark Nussmeier , Nicholas Högasten , Theodore R. Hoelter , Katrin Strandemar , Pierre Boulanger , Barbara Sharp
IPC分类号： G06F1/14
CPC分类号： G06F1/14 , G01R23/00 , G06F1/04 , H04N5/2257 , H04N5/33 , H04N5/365 , H04N5/3765
摘要： Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select the current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.
摘要翻译：提供各种技术来检测诸如成像传感器设备（例如，红外和/或可见光成像设备）的设备中的异常时钟速率。在一个示例中，设备可以包括时钟速率检测电路，其可以容易地集成为设备的一部分，以提供异常时钟速率的有效检测。该装置可以包括斜坡发生器，计数器和/或可以被实现为装置的一部分的其它部件。斜坡发生器可以产生与提供给设备的时钟信号无关的斜坡信号，而计数器可以响应于时钟信号递增或递减计数值。该装置可以包括比较器，适于在斜坡信号达到参考信号时选择计数器的当前计数值。设备的处理器可以适于基于所选择的计数值来确定时钟信号是否在可接受的频率范围内操作。

3. 发明授权

US09762823B2 Imager with increased readout capacitance 有权
公开(公告)号：US09762823B2
公开(公告)日：2017-09-12
申请号：US14543774
申请日：2014-11-17
申请人： FLIR Systems, Inc.
发明人： Brian Simolon , Eric A. Kurth
IPC分类号： H04N5/374 , H04N5/355 , H04N5/378 , H04N5/3745 , H04N5/361
CPC分类号： H04N5/3559 , H04N5/361 , H04N5/37452 , H04N5/37457 , H04N5/378
摘要： An image sensor may be provided. The image sensor may be a high-capacitance image sensor or a dual-mode image sensor having a high-capacitance operational mode. A high-capacitance image sensor may include image detectors and associated unit cells. During operation, the image sensor may integrate image signals from each detector row using unit cells in multiple unit cell rows. The image sensor may integrate and readout image signals in an interleaved process that allows each detector row to capture image data using multiple unit cells. A dual-mode image sensor may operate in a similar manner to a high-capacitance image sensor when operated in the high-capacitance mode. The dual-mode image sensor may have switches interposed between unit cells to selectively couple and decouple the unit cells for switching between the high-capacitance mode and a normal operational mode.

4. 发明申请

US20140184807A1 SEGMENTED FOCAL PLANE ARRAY ARCHITECTURE 有权
公开(公告)号：US20140184807A1
公开(公告)日：2014-07-03
申请号：US14106696
申请日：2013-12-13
申请人： FLIR Systems, Inc.
发明人： Brian Simolon , Eric A. Kurth , Mark Nussmeier , Nicholas Högasten , Theodore R. Hoelter , Katrin Strandemar , Pierre Boulanger , Barbara Sharp
IPC分类号： H04N5/33 , H01L27/146 , H04N5/378
CPC分类号： H04N5/33 , H01L27/14634 , H01L27/1469 , H04N5/2257 , H04N5/378
摘要： Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.
摘要翻译：提供了用于实现红外传感器的分段焦平面阵列（FPA）的各种技术。在一个示例中，系统包括分段的FPA。分段FPA包括具有红外传感器阵列（例如辐射热计）的顶模。顶部管芯还可以包括读出集成电路（ROIC）的一部分。分段FPA还包括具有至少一部分ROIC的底模。顶部和底部管芯通过管芯间连接电耦合。有利地，与常规FPA架构相比，分段FPA可以以更高的产量和更小的占用面积来制造。此外，可以使用针对每个管芯的不同的半导体工艺来制造分段的FPA。

5. 发明授权

US09948878B2 Abnormal clock rate detection in imaging sensor arrays 有权
公开(公告)号：US09948878B2
公开(公告)日：2018-04-17
申请号：US14961829
申请日：2015-12-07
申请人： FLIR Systems, Inc.
发明人： Brian Simolon , Eric A. Kurth , Jim Goodland , Mark Nussmeier , Nicholas Hogasten , Theodore R. Hoelter , Katrin Strandemar , Pierre Boulanger , Barbara Sharp , Naseem Y. Aziz
IPC分类号： G06F11/07 , G01R23/00 , H04N5/376 , H04N5/225 , H04N5/33 , H04N5/365 , G06F1/04
CPC分类号： H04N5/3765 , G01R23/00 , G06F1/04 , G06F11/0703 , G06F11/076 , H04N5/2257 , H04N5/33 , H04N5/365
摘要： Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

6. 发明授权

US09918023B2 Segmented focal plane array architecture 有权
公开(公告)号：US09918023B2
公开(公告)日：2018-03-13
申请号：US14106696
申请日：2013-12-13
申请人： FLIR Systems, Inc.
发明人： Brian Simolon , Eric A. Kurth , Mark Nussmeier , Nicholas Högasten , Theodore R. Hoelter , Katrin Strandemar , Pierre Boulanger , Barbara Sharp
IPC分类号： H04N5/33 , H04N5/378 , H01L27/146 , H04N5/225
CPC分类号： H04N5/33 , H01L27/14634 , H01L27/1469 , H04N5/2257 , H04N5/378
摘要： Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.

7. 发明授权

US09848134B2 Infrared imager with integrated metal layers 有权
公开(公告)号：US09848134B2
公开(公告)日：2017-12-19
申请号：US14092794
申请日：2013-11-27
申请人： FLIR Systems, Inc.
发明人： Brian Simolon , Eric A. Kurth , Steve Barskey , Mark Nussmeier , Nicholas Högasten , Theodore R. Hoelter , Katrin Strandemar , Pierre Boulanger , Barbara Sharp
IPC分类号： H04N9/10 , H04N9/14 , H04N5/33 , H04N5/359 , H01L27/146 , H04N5/365
CPC分类号： H04N5/33 , H01L27/1469 , H04N5/359 , H04N5/365
摘要： Various techniques are provided for implementing, operating, and manufacturing infrared imaging devices using integrated circuits. In one example, a system includes a focal plane array (FPA) integrated circuit comprising an array of infrared sensors adapted to image a scene, a plurality of active circuit components, a first metal layer disposed above and connected to the circuit components, a second metal layer disposed above the first metal layer and connected to the first metal layer, and a third metal layer disposed above the second metal layer and below the infrared sensors. The third metal layer is connected to the second metal layer and the infrared sensors. The first, second, and third metal layers are the only metal layers of the FPA between the infrared sensors and the circuit components. The first, second, and third metal layers are adapted to route signals between the circuit components and the infrared sensors.

8. 发明申请

US20150138367A1 IMAGER WITH INCREASED READOUT CAPACITANCE 有权
标题翻译：具有增加的读取电容的图像
公开(公告)号：US20150138367A1
公开(公告)日：2015-05-21
申请号：US14543774
申请日：2014-11-17
申请人： FLIR Systems, Inc.
发明人： Brian Simolon , Eric A. Kurth
IPC分类号： H04N5/33 , H04N5/378
CPC分类号： H04N5/3559 , H04N5/361 , H04N5/37452 , H04N5/37457 , H04N5/378
摘要： An image sensor may be provided. The image sensor may be a high-capacitance image sensor or a dual-mode image sensor having a high-capacitance operational mode. A high-capacitance image sensor may include image detectors and associated unit cells. During operation, the image sensor may integrate image signals from each detector row using unit cells in multiple unit cell rows. The image sensor may integrate and readout image signals in an interleaved process that allows each detector row to capture image data using multiple unit cells. A dual-mode image sensor may operate in a similar manner to a high-capacitance image sensor when operated in the high-capacitance mode. The dual-mode image sensor may have switches interposed between unit cells to selectively couple and decouple the unit cells for switching between the high-capacitance mode and a normal operational mode.
摘要翻译：可以提供图像传感器。图像传感器可以是具有高电容操作模式的高电容图像传感器或双模式图像传感器。高电容图像传感器可以包括图像检测器和相关联的单元电池。在操作期间，图像传感器可以使用多个单位单元行中的单位单元来集成来自每个检测器行的图像信号。图像传感器可以在交错处理中集成和读出图像信号，其允许每个检测器行使用多个单位单元捕获图像数据。当以高电容模式操作时，双模式图像传感器可以以与高电容图像传感器类似的方式操作。双模式图像传感器可以具有插入在单元电池之间的开关，以选择性地耦合和去耦合单元电池以在高电容模式和正常操作模式之间切换。

9. 发明授权

US11070747B2 Segmented focal plane array architecture 有权
公开(公告)号：US11070747B2
公开(公告)日：2021-07-20
申请号：US15919116
申请日：2018-03-12
申请人： FLIR SYSTEMS, INC.
发明人： Brian Simolon , Eric A. Kurth , Mark Nussmeier , Nicholas Högasten , Theodore R. Hoelter , Katrin Strandemar , Pierre Boulanger , Barbara Sharp
IPC分类号： H04N5/33 , H01L27/146 , H04N5/378 , H04N5/225
摘要： Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.

10. 发明申请

US20160224055A1 ABNORMAL CLOCK RATE DETECTION IN IMAGING SENSOR ARRAYS 有权
标题翻译：成像传感器阵列异常时钟频率检测
公开(公告)号：US20160224055A1
公开(公告)日：2016-08-04
申请号：US14961829
申请日：2015-12-07
申请人： FLIR Systems, Inc.
发明人： Brian Simolon , Eric A. Kurth , Jim Goodland , Mark Nussmeier , Nicholas Hogasten , Theodore R. Hoelter , Katrin Strandemar , Pierre Boulanger , Barbara Sharp , Naseem Y. Aziz
IPC分类号： G06F1/14
CPC分类号： H04N5/3765 , G01R23/00 , G06F1/04 , G06F11/0703 , G06F11/076 , H04N5/2257 , H04N5/33 , H04N5/365
摘要： Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.
摘要翻译：提供各种技术来检测诸如成像传感器设备（例如，红外和/或可见光成像设备）的设备中的异常时钟速率。在一个示例中，设备可以包括时钟速率检测电路，其可以容易地集成为设备的一部分，以提供异常时钟速率的有效检测。该装置可以包括斜坡发生器，计数器和/或可以被实现为装置的一部分的其它部件。斜坡发生器可以产生与提供给设备的时钟信号无关的斜坡信号，而计数器可以响应于时钟信号递增或递减计数值。该装置可以包括比较器，适于在斜坡信号达到参考信号时选择计数器的当前计数值。设备的处理器可以适于基于所选择的计数值来确定时钟信号是否在可接受的频率范围内操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式