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1. 发明授权

US09742513B2 Transmission apparatus and clock regeneration method 有权
公开(公告)号：US09742513B2
公开(公告)日：2017-08-22
申请号：US15165487
申请日：2016-05-26
申请人： FUJITSU LIMITED
发明人： Haruhisa Fukano , Kenichi Ohyama , Toshiharu Hirose , Katsuya Kinoshita
IPC分类号： H04J3/06 , H04J3/07
CPC分类号： H04J3/0691 , H04J3/0623 , H04J3/07
摘要： A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock.

2. 发明授权

US09549231B2 Optical transmission device and OPU frame generation method 有权
标题翻译：光传输设备和OPU帧生成方法
公开(公告)号：US09549231B2
公开(公告)日：2017-01-17
申请号：US14830056
申请日：2015-08-19
申请人： FUJITSU LIMITED
发明人： Haruhisa Fukano , Toshiharu Hirose , Akira Hashimoto , Koji Nekoda , Koichi Kinoshita , Akira Hatae
IPC分类号： H04J14/00 , H04Q11/00 , H04J3/16 , H04J3/07 , H04L12/935
CPC分类号： H04Q11/0003 , H04J3/07 , H04J3/1652 , H04L49/3009 , H04Q2011/0045
摘要： An optical transmission device includes: a serializer and deserializer configured to convert an input client signal into parallel data at a sampling rate of k times (k is a power of 2) a rate of the input client signal and output the parallel data; a frame generation section configured to generate an optical channel payload unit (OPU) frame from the client signal; and a stuff control section connected to an output of the parallel data and configured to perform, in units of 1/k bits, a stuff operation to map the client signal into the OPU frame and thereby calculate a Cn(n=1/k) value which is a theoretical value of the stuff operation.
摘要翻译：光传输装置包括：串行器和解串器，被配置为以k次采样率（k为2的幂）将输入客户端信号转换成并行数据，输入客户端信号的速率并输出并行数据; 帧生成部，被配置为从所述客户端信号生成光信道有效载荷单位（OPU）帧; 以及连接到所述并行数据的输出并且被配置为以1 / k比特为单位执行填充操作以将客户端信号映射到OPU帧中从而计算Cn（n = 1 / k）的填充控制部分，值是作业的理论值。

3. 发明申请

US20190245637A1 TRANSMITTER, RECEIVER, AND CLOCK TRANSFER METHOD 审中-公开
公开(公告)号：US20190245637A1
公开(公告)日：2019-08-08
申请号：US16268223
申请日：2019-02-05
申请人： FUJITSU LIMITED
发明人： Hitomi Toyoda , EIJI GOBARU , Haruhisa Fukano , Takuya Nishioka , Atsunori MACHIDA
IPC分类号： H04J3/06 , H04L7/04 , H04L7/00
CPC分类号： H04J3/0635 , H04L7/0008 , H04L7/04
摘要： A transmitter includes a memory, and a processor configured to generate a first clock parallel signal by performing serial-parallel conversion of a first clock signal acquired by using a reference clock and generate a second clock parallel signal by performing serial-parallel conversion of a second clock signal acquired by using the reference clock, generate first compressed information by compressing the first clock parallel signal on the basis of clock periodicity and generate second compressed information by compressing the second clock parallel signal based on the clock periodicity, generate a serial signal by adding a synchronization signal indicating a top of a multiplexed signal to the multiplexed signal generated by time-division multiplexing of the first compressed information and the second compressed information, and transmit the serial signal to a receiver.

4. 发明授权

US11303376B2 Information processing apparatus and time synchronization method 有权
公开(公告)号：US11303376B2
公开(公告)日：2022-04-12
申请号：US16876220
申请日：2020-05-18
申请人： FUJITSU LIMITED
发明人： Shiryu Oe , Tsutomu Noguchi , Haruhisa Fukano , Akihiro Kuwabara
IPC分类号： H04J3/06
摘要： A non-transitory computer-readable recording medium storing a program that causes a computer to execute a time synchronization process between a master device and a slave device, the process includes calculating a clock deviation between the master device and the slave device based on a plurality of pieces of time information in each of the master device and the slave device, dividing a difference in the clock deviation, and incorporating each of the divided differences into the time information of the slave device to correct the clock deviation.

5. 发明授权

US11057135B2 Transmitter, receiver, and clock transfer method 有权
公开(公告)号：US11057135B2
公开(公告)日：2021-07-06
申请号：US16268223
申请日：2019-02-05
申请人： FUJITSU LIMITED
发明人： Hitomi Toyoda , Eiji Gobaru , Haruhisa Fukano , Takuya Nishioka , Atsunori Machida
IPC分类号： H04J3/06 , H04L7/00 , H04L7/04
摘要： A transmitter includes a memory, and a processor configured to generate a first clock parallel signal by performing serial-parallel conversion of a first clock signal acquired by using a reference clock and generate a second clock parallel signal by performing serial-parallel conversion of a second clock signal acquired by using the reference clock, generate first compressed information by compressing the first clock parallel signal on the basis of clock periodicity and generate second compressed information by compressing the second clock parallel signal based on the clock periodicity, generate a serial signal by adding a synchronization signal indicating a top of a multiplexed signal to the multiplexed signal generated by time-division multiplexing of the first compressed information and the second compressed information, and transmit the serial signal to a receiver.

6. 发明申请

US20200382233A1 INFORMATION PROCESSING APPARATUS AND TIME SYNCHRONIZATION METHOD 审中-公开
公开(公告)号：US20200382233A1
公开(公告)日：2020-12-03
申请号：US16876220
申请日：2020-05-18
申请人： FUJITSU LIMITED
发明人： Shiryu Oe , Tsutomu Noguchi , Haruhisa Fukano , Akihiro Kuwabara
IPC分类号： H04J3/06
摘要： A non-transitory computer-readable recording medium storing a program that causes a computer to execute a time synchronization process between a master device and a slave device, the process includes calculating a clock deviation between the master device and the slave device based on a plurality of pieces of time information in each of the master device and the slave device, dividing a difference in the clock deviation, and incorporating each of the divided differences into the time information of the slave device to correct the clock deviation.

7. 发明申请

US20160373245A1 TRANSMISSION APPARATUS AND CLOCK REGENERATION METHOD 有权
标题翻译：传输装置和时钟再生方法
公开(公告)号：US20160373245A1
公开(公告)日：2016-12-22
申请号：US15165487
申请日：2016-05-26
申请人： FUJITSU LIMITED
发明人： Haruhisa Fukano , Kenichi Ohyama , Toshiharu Hirose , Katsuya Kinoshita
IPC分类号： H04L7/033
CPC分类号： H04J3/0691 , H04J3/0623 , H04J3/07
摘要： A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock.
摘要翻译：一种发送装置，被配置为从接收信号中提取接收数据和第一时钟，并且基于与第一时钟同步的第二时钟发送接收数据，发送装置包括：检测器，被配置为检测第一时钟与第第二个时钟选择器，被配置为根据与通过将由连续“0”和连续“1”的比特形成的比特模式相互不同的比特移位的多个并行数据的频率差来选择并行数据，以及转换器配置将由选择器选择的并行数据转换为串行数据，以便成为第二个时钟。

8. 发明申请

US20140321851A1 TRANSMISSION DEVICE AND SYNCHRONIZATION CONTROL METHOD 审中-公开
标题翻译：传输设备和同步控制方法
公开(公告)号：US20140321851A1
公开(公告)日：2014-10-30
申请号：US14222884
申请日：2014-03-24
申请人： FUJITSU LIMITED
发明人： Toshiharu HIROSE , Kenichi Ohyama , Akira Hashimoto , Haruhisa Fukano
IPC分类号： H04B10/27
CPC分类号： H04B10/27 , H04J3/0602 , H04J3/0691 , H04J3/1611 , H04Q2213/13097 , H04Q2213/1331
摘要： A transmission device includes: a detector to detect a head pattern indicating a head of data for each of ports that receives the data; a write controller to write the data to a memory provided for each of the ports, based on a detection timing of the head pattern detected by the detector; a determination unit to determine, among ports for each of which the head pattern has been detected by the detector, a specific port for which a total delay amount is minimum, the total delay amount being a total sum of delay amounts from the head pattern related to the specific port to each of the head patterns related to ports other than the specific port; and a read controller to read the data from the memory, based on the detection timing of the head pattern related to the specific port determined by the determination unit.
摘要翻译：发送装置包括：检测器，用于检测指示用于接收数据的每个端口的数据头部的头部模式; 写入控制器，用于基于由检测器检测到的头部图案的检测定时将数据写入到为每个端口提供的存储器; 确定单元，用于在所述检测器检测到所述头部图案的端口中确定总延迟量最小的特定端口，所述总延迟量是与所述头部模式相关的延迟量的总和到与特定端口以外的端口相关的每个头部模式的特定端口; 以及读取控制器，用于基于由确定单元确定的与特定端口相关的头部图案的检测定时来从存储器读取数据。

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