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1. 发明授权

US10248479B2 Arithmetic processing device storing diagnostic results in parallel with diagnosing, information processing apparatus and control method of arithmetic processing device 有权
公开(公告)号：US10248479B2
公开(公告)日：2019-04-02
申请号：US15150474
申请日：2016-05-10
申请人： FUJITSU LIMITED
发明人： Makoto Suga , Akio Tokoyoda , Masatoshi Aihara , Koji Hosoe , Koichiro Takayama
IPC分类号： G06F11/273 , G06F11/00 , G11C29/12 , G11C29/26 , G11C29/36 , G11C29/44 , G11C29/46 , G11C29/56
摘要： The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.

2. 发明授权

US10078602B2 Information processing apparatus, memory controller, and memory control method 有权
公开(公告)号：US10078602B2
公开(公告)日：2018-09-18
申请号：US15095203
申请日：2016-04-11
申请人： FUJITSU LIMITED
发明人： Akio Tokoyoda , Masatoshi Aihara , Koichiro Takayama , Koji Hosoe
IPC分类号： G06F13/36 , G06F13/38 , G06F13/16
CPC分类号： G06F13/1673 , G06F13/1642
摘要： An information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.

3. 发明申请

US20160342541A1 INFORMATION PROCESSING APPARATUS, MEMORY CONTROLLER, AND MEMORY CONTROL METHOD 审中-公开
标题翻译：信息处理装置，存储器控制器和存储器控制方法
公开(公告)号：US20160342541A1
公开(公告)日：2016-11-24
申请号：US15095203
申请日：2016-04-11
申请人： FUJITSU LIMITED
发明人： Akio Tokoyoda , Masatoshi Aihara , Koichiro Takayama , Koji Hosoe
IPC分类号： G06F13/16
CPC分类号： G06F13/1673 , G06F13/1642
摘要： An information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.
摘要翻译：一种信息处理装置，包括：存储装置，被配置为存储数据; 算术处理器，被配置为发出要发送到存储器件的请求; 以及存储器控制器，包括：缓冲器，被配置为存储由所述算术处理处理器发出且未被选择的一个或多个未选择的请求; 历史寄存器，被配置为保存已被发送到存储器设备的一个或多个发送请求的一个或多个地址; 以及选择单元，被配置为基于存储在历史寄存器中的一个或多个地址从存储在缓冲器中的一个或多个未选择的请求中选择要发送到存储器设备的目标请求，并将目标请求发送到存储器设备。

4. 发明授权

US10230625B2 Information processing apparatus, information processing system, and communication device 有权
公开(公告)号：US10230625B2
公开(公告)日：2019-03-12
申请号：US14924168
申请日：2015-10-27
申请人： FUJITSU LIMITED
发明人： Masahiro Maeda , Koichiro Takayama , Tomohiro Inoue , Shinya Hiramoto , Shun Ando , Yuichiro Ajima
IPC分类号： H04L12/703 , H04L12/707 , H04L12/26 , G06F13/42 , G06F11/00 , G06F11/07 , H04L1/18 , G06F15/76
摘要： An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

5. 发明申请

US20160191376A1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND COMMUNICATION DEVICE 审中-公开
标题翻译：信息处理装置，信息处理系统和通信装置
公开(公告)号：US20160191376A1
公开(公告)日：2016-06-30
申请号：US14924168
申请日：2015-10-27
申请人： FUJITSU LIMITED
发明人： Masahiro Maeda , Koichiro Takayama , Tomohiro Inoue , Shinya Hiramoto , Shun Ando , Yuichiro Ajima
IPC分类号： H04L12/703 , H04L12/26 , H04L12/707
CPC分类号： H04L45/28 , G06F11/004 , G06F11/0745 , G06F11/0751 , G06F11/0793 , G06F13/4282 , G06F15/76 , H04L1/188 , H04L43/0823 , H04L45/22
摘要： An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.
摘要翻译：一种信息处理装置，包括：运算处理单元; 以及通信装置，被配置为通过多个第一车道从另一信息处理装置接收数据，并将所接收的数据输出到所述运算处理单元，其中，所述通信装置包括检测所述多个第一车道的故障的检测单元; 以及控制单元，其基于劣化请求执行停止使用所述多个第一车道中的任一个的第一退化处理，基于所述第一退化处理，基于所述第一通道停止使用已停止的第一车道的恢复处理恢复请求，并且在恢复处理中，当检测单元检测到已经恢复使用的第一车道的故障时，执行停止使用已经恢复使用的第一车道的第二劣化处理。

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