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1. 发明授权

US09766820B2 Arithmetic processing device, information processing device, and control method of arithmetic processing device 有权
公开(公告)号：US09766820B2
公开(公告)日：2017-09-19
申请号：US14708331
申请日：2015-05-11
申请人： FUJITSU LIMITED
发明人： Yuta Toyoda , Koji Hosoe , Masatoshi Aihara , Akio Tokoyoda , Makoto Suga
IPC分类号： G06F12/00 , G06F3/06 , G06F12/0802 , G06F12/0855 , G06F12/0879 , G06F12/0831
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0658 , G06F3/0673 , G06F12/0802 , G06F12/0831 , G06F12/0859 , G06F12/0879 , G06F2212/1024 , G06F2212/251 , G06F2212/301 , G06F2212/50
摘要： An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.

2. 发明申请

US20150339062A1 ARITHMETIC PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD OF ARITHMETIC PROCESSING DEVICE 有权
标题翻译：算术处理装置，信息处理装置以及算术处理装置的控制方法
公开(公告)号：US20150339062A1
公开(公告)日：2015-11-26
申请号：US14708331
申请日：2015-05-11
申请人： FUJITSU LIMITED
发明人： Yuta Toyoda , Koji HOSOE , Masatoshi Aihara , AKIO TOKOYODA , Makoto SUGA
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0658 , G06F3/0673 , G06F12/0802 , G06F12/0831 , G06F12/0859 , G06F12/0879 , G06F2212/1024 , G06F2212/251 , G06F2212/301 , G06F2212/50
摘要： An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.
摘要翻译：一种连接到主存储器的算术处理装置，所述算术处理器包括存储数据的高速缓存存储器，对存储在所述高速缓冲存储器中的数据执行算术运算的算术单元，控制所述高速缓冲存储器并输出第一请求，其读取存储在主存储器中的数据;以及第二控制装置，其连接到主存储器，并且发送分配了从第一控制装置输出的第一请求的多个第二请求，接收与多个从主存储器发送的第二请求，并将每个数据发送到第一控制装置。

3. 发明申请

US20150149675A1 MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING MEMORY CONTROLLER 有权
标题翻译：记忆控制器，信息处理装置和控制存储器控制器的方法
公开(公告)号：US20150149675A1
公开(公告)日：2015-05-28
申请号：US14542730
申请日：2014-11-17
申请人： FUJITSU LIMITED
发明人： Yuta Toyoda , Koji HOSOE , AKIO TOKOYODA , Masatoshi Aihara , Makoto SUGA
IPC分类号： G06F13/16 , G06F13/366
CPC分类号： G06F13/1605 , G06F13/161 , G06F13/366
摘要： A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.
摘要翻译：存储器控制器具有保持写请求和读请求的请求保持单元; 发送单元，通过发送总线将写入请求和读取请求中的任一个发送到存储器; 接收单元，通过接收总线接收对应于读取请求的读取数据; 以及请求仲裁单元，执行：当第一接收时间不晚于第二接收时间时，在所述读取请求之前发送所述写入请求的第一处理，以及在所述写入请求之前发送所述读取请求的第二处理，第一接收时间晚于第二接收时间。第一接收时间是当首先发送写请求时开始读取数据的接收，并且第二接收时间是当首先发送读取请求时开始读取数据的接收。

4. 发明授权

US10248479B2 Arithmetic processing device storing diagnostic results in parallel with diagnosing, information processing apparatus and control method of arithmetic processing device 有权
公开(公告)号：US10248479B2
公开(公告)日：2019-04-02
申请号：US15150474
申请日：2016-05-10
申请人： FUJITSU LIMITED
发明人： Makoto Suga , Akio Tokoyoda , Masatoshi Aihara , Koji Hosoe , Koichiro Takayama
IPC分类号： G06F11/273 , G06F11/00 , G11C29/12 , G11C29/26 , G11C29/36 , G11C29/44 , G11C29/46 , G11C29/56
摘要： The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.

5. 发明申请

US20150149746A1 ARITHMETIC PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, AND A METHOD OF CONTROLLING THE INFORMATION PROCESSING DEVICE 审中-公开
标题翻译：算术处理装置，信息处理装置以及控制信息处理装置的方法
公开(公告)号：US20150149746A1
公开(公告)日：2015-05-28
申请号：US14536763
申请日：2014-11-10
申请人： FUJITSU LIMITED
发明人： Makoto SUGA , AKIO TOKOYODA , Koji HOSOE , Masatoshi Aihara , Yuta Toyoda
IPC分类号： G06F9/30
CPC分类号： G06F12/00 , G06F9/30043 , G06F9/3824 , G06F12/023 , G06F13/00 , G06F2212/1024 , G06F2212/401 , G06F2212/502
摘要： An arithmetic processing device promotes transmission efficiency between a processor and a memory. The arithmetic processing device has an arithmetic processing unit which issues an instruction accompanying with data which is sent to the memory, a judgment unit which judges whether or not a redundancy degree of the data which is accompanied with the instruction is more than a predetermined value, a compression unit which judges whether or not compress the data based on an waiting time and a compression time when the redundancy degree of the data is more than the predetermined value, and compress the data when judging that performs the compression, and an instruction arbitration unit which transfers the instruction accompanying with the compressed data to the memory when the compression unit performs the compression and transfers the instruction accompanying with the non-compressed data to the memory when the compression unit does not perform the compression.
摘要翻译：算术处理装置提高处理器和存储器之间的传输效率。算术处理装置具有运算处理单元，该运算处理单元发出伴随着发送给存储器的数据的指令，判断单元判断伴随该指令的数据的冗余度是否大于预定值，压缩单元，其基于当数据的冗余度大于预定值时的等待时间和压缩时间来判断是否压缩数据，并且在执行压缩的判定时压缩数据;以及指令仲裁单元当压缩单元执行压缩时，将压缩数据附带的指令传送到存储器，并且当压缩单元不执行压缩时，将伴随非压缩数据的指令传送到存储器。

6. 发明申请

US20150089281A1 MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS 有权
标题翻译：记忆控制器，信息处理装置以及控制信息处理装置的方法
公开(公告)号：US20150089281A1
公开(公告)日：2015-03-26
申请号：US14447671
申请日：2014-07-31
申请人： FUJITSU LIMITED
发明人： Akio Tokoyoda , Yuta Toyoda , Makoto Suga , Masatoshi Aihara , Koji Hosoe
IPC分类号： G06F11/14 , G06F11/07
CPC分类号： G06F11/073 , G06F11/0763 , G06F11/0772 , G06F11/1048 , G06F13/00
摘要： A memory controller is provided between a CPU and a main memory, controls access from the CPU to the main memory, and includes a data storage area and a controller. In a case where error information indicating that an error occurs is included in write data from the CPU to the main memory, the controller stores the write data in a data storage area in association with a writing destination address. Therefore, even in a case where the error information is not written in the main memory, the error information can be recorded.
摘要翻译：在CPU和主存储器之间提供存储控制器，控制从CPU到主存储器的访问，并且包括数据存储区域和控制器。在从CPU向主存储器的写入数据中包含指示发生错误的错误信息的情况下，控制器将写入数据与写入目的地地址相关联地存储在数据存储区域中。因此，即使在主存储器中未写入错误信息的情况下，也可以记录错误信息。

7. 发明授权

US09645818B2 Information processing apparatus and control method of information processing apparatus 有权
公开(公告)号：US09645818B2
公开(公告)日：2017-05-09
申请号：US14868452
申请日：2015-09-29
申请人： FUJITSU LIMITED
发明人： Makoto Suga , Koji Hosoe , Akio Tokoyoda , Masatoshi Aihara , Yuta Toyoda
IPC分类号： G06F12/00 , G06F9/30 , G06F11/00
CPC分类号： G06F9/3001 , G06F11/00 , G06F11/0727 , G06F11/079
摘要： The information processing apparatus includes an arithmetic processing device configured to output an access request, a storage device configured to store data, a storage control device configured to accept the access request to the storage device from the arithmetic processing device, transfer the accepted access request to the storage device, and acquire a response to the access request from the storage device, and a diagnosis control device configured to send an access request to the storage device to the storage control device in place of the access request to the storage device from the arithmetic processing device, and acquire a response from the storage device via the storage control device.

8. 发明授权

US09612891B2 Memory controller, information processing apparatus, and method of controlling information processing apparatus 有权
公开(公告)号：US09612891B2
公开(公告)日：2017-04-04
申请号：US14447671
申请日：2014-07-31
申请人： FUJITSU LIMITED
发明人： Akio Tokoyoda , Yuta Toyoda , Makoto Suga , Masatoshi Aihara , Koji Hosoe
IPC分类号： G06F11/00 , G06F11/07 , G06F13/00 , G06F11/10
CPC分类号： G06F11/073 , G06F11/0763 , G06F11/0772 , G06F11/1048 , G06F13/00
摘要： A memory controller is provided between a CPU and a main memory, controls access from the CPU to the main memory, and includes a data storage area and a controller. In a case where error information indicating that an error occurs is included in write data from the CPU to the main memory, the controller stores the write data in a data storage area in association with a writing destination address. Therefore, even in a case where the error information is not written in the main memory, the error information can be recorded.

9. 发明申请

US20180336132A1 INFORMATION PROCESSING DEVICE, PROCESSOR, AND TRANSMISSION INFORMATION STORAGE METHOD 审中-公开
公开(公告)号：US20180336132A1
公开(公告)日：2018-11-22
申请号：US15983237
申请日：2018-05-18
申请人： FUJITSU LIMITED
发明人： Makoto SUGA , Koji HOSOE , Masatoshi Aihara
IPC分类号： G06F12/0811 , G06F12/10
摘要： An apparatus includes a memory; and a processor that includes a memory-controller that controls transmission-and-reception of information to and from the memory, wherein the memory-controller comprises a buffer that includes storage-regions, a control-circuit that stores, in one of the storage-regions, information that operates the memory among pieces of information transmitted to the memory, a counter that counts a number of pieces of second information transmitted to the memory, the second information being information transmitted to the memory since the information is transmitted to the memory until the next information is transmitted to the memory and indicating no-transmission of the information, a second buffer that includes a second storage-regions respectively corresponding to the storage-regions, and a second control-circuit that stores a count value of the counter in one of the second storage-regions in association with the information stored in the storage region.

10. 发明授权

US09785579B2 Memory controller, information processing apparatus, and method of controlling memory controller 有权
公开(公告)号：US09785579B2
公开(公告)日：2017-10-10
申请号：US14542730
申请日：2014-11-17
申请人： FUJITSU LIMITED
发明人： Yuta Toyoda , Koji Hosoe , Akio Tokoyoda , Masatoshi Aihara , Makoto Suga
IPC分类号： G06F13/36 , G06F13/00 , G06F13/16 , G06F13/366
CPC分类号： G06F13/1605 , G06F13/161 , G06F13/366
摘要： A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.

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