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1. 发明申请

US20160180968A1 MEMORY DEVICE, STORAGE APPARATUS AND METHOD FOR DIAGNOSING STORAGE APPARATUS 有权
标题翻译：存储装置，存储装置和用于诊断存储装置的方法
公开(公告)号：US20160180968A1
公开(公告)日：2016-06-23
申请号：US14924779
申请日：2015-10-28
申请人： FUJITSU LIMITED
发明人： MICHIYO GARBE , Masahiro Ise , Osamu Ishibashi , YOSHINORI MESAKI
IPC分类号： G11C29/50
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/349 , G11C29/50004 , G11C29/50016 , G11C2029/0409 , G11C2029/5004
摘要： A memory device comprises a memory block including a plurality of cells each including an erase state and a program state, respectively; and a control circuit configured to execute, in response to a program command, program operation of applying a pulse to each cell to charge an electric charge and transferring the cell from the erase state to the program state. The control circuit executes, in response to a diagnostic command, diagnostic operation of applying to a diagnostic target cell the pulse within a range that the diagnostic target cell in the erase state in a memory block including stored data is not shifted to the program state, and checking whether or not a charge speed of the diagnostic target cell is faster than or equal to a charge speed of a slowest-speed cell whose charge speed is the slowest among normal cells.
摘要翻译：存储器件包括分别包括多个单元的存储器块，每个单元包括擦除状态和程序状态; 以及控制电路，被配置为响应于程序命令执行向每个单元施加脉冲以对电荷充电并将所述单元从擦除状态传送到所述程序状态的编程操作。控制电路响应于诊断命令执行向诊断目标单元施加包括存储数据的存储块中的擦除状态下的诊断目标单元没有转移到程序状态的范围内的脉冲的诊断操作，并且检查诊断对象单元的充电速度是否快于或等于正常单元中充电速度最慢的最慢速单元的充电速度。

2. 发明申请

US20190035469A1 MEMORY CONTROL CIRCUIT, MEMORY, AND MEMORY CONTROL METHOD 审中-公开
公开(公告)号：US20190035469A1
公开(公告)日：2019-01-31
申请号：US16037385
申请日：2018-07-17
申请人： FUJITSU LIMITED
发明人： Masahiro Ise , Masazumi MAEDA
IPC分类号： G11C16/10 , G11C11/56 , G11C7/10
摘要： A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.

3. 发明申请

US20170301401A1 MEMORY AND MEMORY CONTROL METHOD 有权
公开(公告)号：US20170301401A1
公开(公告)日：2017-10-19
申请号：US15465700
申请日：2017-03-22
申请人： FUJITSU LIMITED
发明人： Masazumi MAEDA , Masahiro Ise
IPC分类号： G11C16/16 , G11C16/10 , G11C16/26 , G11C16/34
CPC分类号： G11C16/16 , G11C5/144 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.

4. 发明授权

US10002670B2 Memory and memory control method 有权
公开(公告)号：US10002670B2
公开(公告)日：2018-06-19
申请号：US15465700
申请日：2017-03-22
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda , Masahiro Ise
IPC分类号： G11C16/16 , G11C16/10 , G11C16/34 , G11C16/26
CPC分类号： G11C16/16 , G11C5/144 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.

5. 发明授权

US09508421B2 Memory device, storage apparatus and method for diagnosing slow memory cells 有权
标题翻译：用于诊断慢速存储器单元的存储器件，存储装置和方法
公开(公告)号：US09508421B2
公开(公告)日：2016-11-29
申请号：US14924779
申请日：2015-10-28
申请人： FUJITSU LIMITED
发明人： Michiyo Garbe , Masahiro Ise , Osamu Ishibashi , Yoshinori Mesaki
IPC分类号： G11C11/56 , G11C16/12 , G11C29/50
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/349 , G11C29/50004 , G11C29/50016 , G11C2029/0409 , G11C2029/5004
摘要： A memory device comprises a memory block including a plurality of cells each including an erase state and a program state, respectively; and a control circuit configured to execute, in response to a program command, program operation of applying a pulse to each cell to charge an electric charge and transferring the cell from the erase state to the program state. The control circuit executes, in response to a diagnostic command, diagnostic operation of applying to a diagnostic target cell the pulse within a range that the diagnostic target cell in the erase state in a memory block including stored data is not shifted to the program state, and checking whether or not a charge speed of the diagnostic target cell is faster than or equal to a charge speed of a slowest-speed cell whose charge speed is the slowest among normal cells.
摘要翻译：存储器件包括分别包括多个单元的存储器块，每个单元包括擦除状态和程序状态; 以及控制电路，被配置为响应于程序命令执行向每个单元施加脉冲以对电荷充电并将所述单元从擦除状态传送到所述程序状态的编程操作。控制电路响应于诊断命令执行向诊断目标单元施加包括存储数据的存储块中的擦除状态下的诊断目标单元没有转移到程序状态的范围内的脉冲的诊断操作，并且检查诊断对象单元的充电速度是否快于或等于正常单元中充电速度最慢的最慢速单元的充电速度。

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