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1. 发明授权

US10002670B2 Memory and memory control method 有权
公开(公告)号：US10002670B2
公开(公告)日：2018-06-19
申请号：US15465700
申请日：2017-03-22
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda , Masahiro Ise
IPC分类号： G11C16/16 , G11C16/10 , G11C16/34 , G11C16/26
CPC分类号： G11C16/16 , G11C5/144 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.

2. 发明授权

US09571110B2 Delay circuit, delay locked loop circuit including delay circuit and processor including delay locked loop circuit 有权
标题翻译：延迟电路，延迟锁定环路电路，包括延迟电路和处理器，包括延迟锁定环路电路
公开(公告)号：US09571110B2
公开(公告)日：2017-02-14
申请号：US14835769
申请日：2015-08-26
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda , Yoshiharu Yoshizawa
IPC分类号： H03L7/06 , H03L7/095 , H03K5/134 , H03L7/081 , H03K5/00
CPC分类号： H03L7/095 , H03K5/134 , H03K2005/00019 , H03L7/0818
摘要： A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of variably controlling a delay amount; a variable control voltage generator circuit configured to supply, to a first delay unit included in each of the plurality of delay buffers, a variable control voltage provided to control the delay amount of the first delay unit; and a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling the delay amount of the second delay unit. The plurality of delay buffers are connected in series and an input signal propagates through the plurality of serially connected delay buffers.
摘要翻译：延迟电路包括多个延迟缓冲器，每个延迟缓冲器包括两个或多个串联的延迟单元，每个延迟单元能够可变地控制延迟量; 可变控制电压发生器电路，被配置为向包括在所述多个延迟缓冲器中的每个延迟缓冲器中的第一延迟单元提供用于控制所述第一延迟单元的延迟量的可变控制电压; 以及固定控制电压发生器电路，被配置为向所述多个延迟缓冲器中的每一个中包括的第二延迟单元提供用于控制所述第二延迟单元的延迟量的多个固定控制电压之间的固定控制电压。多个延迟缓冲器串联连接，并且输入信号通过多个串行连接的延迟缓冲器传播。

3. 发明授权

US10409686B2 Apparatus and method to determine plural locations in communication circuits at which failures have occurred 有权
公开(公告)号：US10409686B2
公开(公告)日：2019-09-10
申请号：US15792868
申请日：2017-10-25
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda , Koji Migita
IPC分类号： G06F11/14 , G06F11/22 , H04L12/939 , H04L12/933
摘要： An apparatus includes first and second circuits that transmit and receive information to and from each other through first paths, where each of the first and second circuits includes second paths respectively coupled to the first paths, and matrix switches that are provided across the second paths and switch a transmission path of information transmitted to any one of the second paths. Upon detecting an error in the second paths, the apparatus conducts a loop-back test in which each matrix switch is switched to a loop-back state in which information to be transmitted to the second path in which the error has been detected, is looped back. Upon detecting an error in the loop-back test, the apparatus switches the matrix switches to a bypass state in which the second path in which the error is detected is bypassed to another one of the second paths to continue the loop-back test.

4. 发明授权

US10249371B2 Control circuit, semiconductor storage device, and method of controlling semiconductor storage device 有权
公开(公告)号：US10249371B2
公开(公告)日：2019-04-02
申请号：US15718029
申请日：2017-09-28
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda
IPC分类号： G11C16/00 , G11C16/04 , G11C16/10 , G11C16/28 , G11C29/00 , G11C29/44 , G11C29/52 , G06F12/02 , G11C11/56
摘要： A control circuit that controls a memory including a storage region and a redundant region, the control circuit includes a detector that detects a defective block in the memory, and a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme.

5. 发明授权

US10720202B2 Apparatus for memory control 有权
公开(公告)号：US10720202B2
公开(公告)日：2020-07-21
申请号：US16536360
申请日：2019-08-09
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda , Kazuko Higurashi
IPC分类号： G11C11/40 , G11C11/409 , G11C29/52 , G06F13/16 , G11C11/4074 , G11C11/4078
摘要： An apparatus for memory control includes a data storage area configured to store data indicative of a distribution of total current consumption required for a write operation as measured with respect to one or more nonvolatile memory devices of a first type, and a control apparatus configured to evaluate, based on the data indicative of the distribution, a degree to which a total amount of current consumption required for a write operation with respect to a memory area in a nonvolatile memory device of the same first type, regarding a current flowing from a power supply to the nonvolatile memory device during the write operation, is deviated toward larger total current consumptions in the distribution, thereby determining whether the memory area is satisfactory.

6. 发明授权

US10256798B2 Test method of delay circuit including delay line 有权
公开(公告)号：US10256798B2
公开(公告)日：2019-04-09
申请号：US15344722
申请日：2016-11-07
申请人： FUJITSU LIMITED
发明人： Noriyuki Tokuhiro , Masazumi Maeda
IPC分类号： G01R31/28 , H03K5/13 , H03K5/133 , H03K5/00
摘要： A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.

7. 发明授权

US09362877B2 Electronic component, information processing apparatus, and electronic component control method 有权
标题翻译：电子元件，信息处理装置和电子元件控制方法
公开(公告)号：US09362877B2
公开(公告)日：2016-06-07
申请号：US14275111
申请日：2014-05-12
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda , Yoshiharu Yoshizawa
IPC分类号： H03G3/00 , H03K19/094 , H03G1/00
CPC分类号： H03G3/004 , H03G1/0029 , H03K19/09432
摘要： An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.
摘要翻译：电子部件包括：第一放大器，被配置为放大差分信号之一; 第二放大器，被配置为放大所述差分信号中的另一个; 传感器，被配置为测量从第一放大器输出的第一输出信号的电压和从第二放大器输出的第二输出信号; 以及控制器，其被配置为基于由所述传感器测量的电压来控制所述第一放大器的电流值和电阻值中的一个或两者，使得所述第一输出信号的公共电压和所述第二输出信号的公共电压相互近似。

8. 发明申请

US20180137008A1 APPARATUS AND METHOD TO DETERMINE PLURAL LOCATIONS IN COMMUNICATION CIRCUITS AT WHICH FAILURES HAVE OCCURRED 审中-公开
公开(公告)号：US20180137008A1
公开(公告)日：2018-05-17
申请号：US15792868
申请日：2017-10-25
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda , Koji Migita
IPC分类号： G06F11/14 , G06F11/22 , H04L12/939
CPC分类号： G06F11/1423 , G06F11/22 , G06F2201/85 , H04L49/1515 , H04L49/552 , H04L49/555 , H04L49/557
摘要： An apparatus includes first and second circuits that transmit and receive information to and from each other through first paths, where each of the first and second circuits includes second paths respectively coupled to the first paths, and matrix switches that are provided across the second paths and switch a transmission path of information transmitted to any one of the second paths. Upon detecting an error in the second paths, the apparatus conducts a loop-back test in which each matrix switch is switched to a loop-back state in which information to be transmitted to the second path in which the error has been detected, is looped back. Upon detecting an error in the loop-back test, the apparatus switches the matrix switches to a bypass state in which the second path in which the error is detected is bypassed to another one of the second paths to continue the loop-back test.

9. 发明授权

US09742413B2 Electronic device and information processing apparatus 有权
公开(公告)号：US09742413B2
公开(公告)日：2017-08-22
申请号：US14743153
申请日：2015-06-18
申请人： FUJITSU LIMITED
发明人： Yoshiharu Yoshizawa , Masazumi Maeda
IPC分类号： H03L7/08 , H03L7/081
CPC分类号： H03L7/0816
摘要： An electronic device includes: a voltage controlled delay line including delay elements configured to delay an input clock signal and output the clock signal, a delay control element configured to control a delay time of the clock signal delayed by the delay elements in accordance with a control voltage, a delay sensitivity adjustment circuit configured to adjust a ratio of an amount of change of the delay time to an amount of change of the control voltage, and a plurality of delay circuits; and a control voltage generation circuit configured to compare a phase of an output signal of any one of the plurality of delay circuits and a phase of the clock signal, generate the control voltage so as to match the phase of the output signal and the phase of the clock signal based on the comparison result, and output the control voltage to the delay control element.

10. 发明申请

US20150002205A1 ELECTRONIC COMPONENT, INFORMATION PROCESSING APPARATUS, AND ELECTRONIC COMPONENT CONTROL METHOD 有权
标题翻译：电子元件，信息处理设备和电子元件控制方法
公开(公告)号：US20150002205A1
公开(公告)日：2015-01-01
申请号：US14275111
申请日：2014-05-12
申请人： FUJITSU LIMITED
发明人： Masazumi Maeda , Yoshiharu Yoshizawa
IPC分类号： H03K3/013 , H03G3/00
CPC分类号： H03G3/004 , H03G1/0029 , H03K19/09432
摘要： An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.
摘要翻译：电子部件包括：第一放大器，被配置为放大差分信号之一; 第二放大器，被配置为放大所述差分信号中的另一个; 传感器，被配置为测量从第一放大器输出的第一输出信号的电压和从第二放大器输出的第二输出信号; 以及控制器，其被配置为基于由所述传感器测量的电压来控制所述第一放大器的电流值和电阻值中的一个或两者，使得所述第一输出信号的公共电压和所述第二输出信号的公共电压相互近似。

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