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1. 发明申请

US20210216867A1 INFORMATION PROCESSING APPARATUS, NEURAL NETWORK COMPUTATION PROGRAM, AND NEURAL NETWORK COMPUTATION METHOD 有权
公开(公告)号：US20210216867A1
公开(公告)日：2021-07-15
申请号：US17104003
申请日：2020-11-25
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai
IPC分类号： G06N3/08 , G06N3/04
摘要： A processor quantizes a plurality of first intermediate data obtained from a training into intermediate data of a first fixed-point number according to a first fixed-point number format, obtains a first quantization error between the first intermediate data and the intermediate data of the first fixed-point number, quantizes the first intermediate data into intermediate data of a second fixed-point number according to a second fixed-point number format, and obtains a second quantization error between the first intermediate data and the intermediate data of the second fixed-point number. The processor compares the first quantization error with the second quantization error and determine as a determined fixed-point number format the fixed-point number format having the lower of the quantization errors, and executes the training operation with intermediate data of a fixed-point number obtained by quantizing the plurality of first intermediate data according to the determined fixed-point number format.

2. 发明申请

US20210097397A1 INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD 有权
公开(公告)号：US20210097397A1
公开(公告)日：2021-04-01
申请号：US17017751
申请日：2020-09-11
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai
IPC分类号： G06N3/08 , G06N3/04
摘要： An information processing apparatus includes: a memory; and a processor configured to: execute a predetermined operation on each of pieces of input data so as to generate pieces of first operation result data that is a result of the predetermined operation; acquire statistical information regarding a distribution of digits of most significant bits that are unsigned for each of the pieces of first operation result data; store the pieces of first operation result data based on a predetermined data type in a register; execute a saturation process or a rounding process on the pieces of first operation result data based on, out of a first data type and a second data type that represent operation result data with a predetermined bit width, the second data type having a narrower bit width than the first data type, so as to generate a pieces of second operation result data.

3. 发明授权

US10727795B2 Amplifier circuit that amplifies differential signal and optical module that includes amplifier circuit 有权
公开(公告)号：US10727795B2
公开(公告)日：2020-07-28
申请号：US15922973
申请日：2018-03-16
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai
IPC分类号： H03F3/45 , H03F1/02 , H04B10/516 , H03F1/08 , H03F3/08 , H04B10/40
摘要： An amplifier circuit includes: an amplifier; and a bias circuit that controls an operation point of the amplifier. The amplifier includes: a load resistor; a differential transistor pair electrically coupled to the load resistor; and a tail transistor electrically coupled to the differential transistor pair. The bias circuit includes: a voltage generator circuit that generates a reference voltage corresponding to a sum of a threshold voltage of a transistor in the differential transistor pair and a saturation drain voltage of the tail transistor; and a current generator circuit that generates a reference current that is proportional to a difference between a power supply voltage of the amplifier circuit and the reference voltage by using a reference resistor. The current generator circuit is electrically coupled to the amplifier such that a tail current that flows through the tail transistor is proportional to the reference current.

4. 发明申请

US20190312757A1 DECISION FEEDBACK EQUALIZER AND INTERCONNECT CIRCUIT 审中-公开
公开(公告)号：US20190312757A1
公开(公告)日：2019-10-10
申请号：US16451225
申请日：2019-06-25
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai
IPC分类号： H04L25/03 , H03K5/24 , H03K3/037 , H03K5/003
摘要： A decision feedback equalizer includes: a comparison circuit; a latch circuit configured to latch a result of comparison by the comparison circuit; a setting circuit configured to set a decision threshold of the comparison circuit in accordance with a control signal; and a switch circuit configured to be controlled to be turned on and off by an output signal from the latch circuit, wherein the setting circuit is configured to be connected in parallel with an input stage of the comparison circuit through the switch circuit and operate in synchronization with a clock signal for driving the comparison circuit.

5. 发明申请

US20180337732A1 DRIVER CIRCUIT, OPTICAL TRANSMISSION MODULE AND OPTICAL TRANSMISSION DEVICE 审中-公开
公开(公告)号：US20180337732A1
公开(公告)日：2018-11-22
申请号：US15969818
申请日：2018-05-03
申请人： FUJITSU LIMITED
发明人： Yuuki Ogata , Toshihiko Mori , Yasufumi Sakai
IPC分类号： H04B10/40 , H01S5/183 , H04B10/80 , H04B10/50 , F21V8/00
CPC分类号： H04B10/40 , G02B6/0006 , H01S5/042 , H01S5/183 , H04B10/504 , H04B10/505 , H04B10/808
摘要： There is provided a driver circuit including a variable current-source configured to include, a first current-source coupled to a first input node to which a first signal is input from an external, a second current-source coupled to a second input node to which a second signal as an inversion of the first signal is input from the external, a first bypass circuit coupled between the first current-source and the first input node, the first bypass circuit being switched according to the second signal, and a second bypass circuit coupled between the second current-source and the second input node, the second bypass circuit being switched according to the first signal, and a terminal circuit configured to be terminated for an optical device driven by a drive signal according to the first signal, the drive signal being output from an output node coupled between the terminal circuit and the variable current-source.

6. 发明申请

US20180316325A1 AMPLIFIER CIRCUIT THAT AMPLIFIES DIFFERENTIAL SIGNAL AND OPTICAL MODULE THAT INCLUDES AMPLIFIER CIRCUIT 审中-公开
公开(公告)号：US20180316325A1
公开(公告)日：2018-11-01
申请号：US15922973
申请日：2018-03-16
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai
IPC分类号： H03F3/45 , H03F1/02 , H04B10/516
CPC分类号： H03F3/45215 , H03F1/0216 , H03F1/0261 , H03F1/086 , H03F3/082 , H03F3/45381 , H03F2200/21 , H03F2200/555 , H03F2203/45022 , H03F2203/45151 , H03F2203/45154 , H03F2203/45178 , H03F2203/45674 , H03F2203/45702 , H04B10/40 , H04B10/516
摘要： An amplifier circuit includes: an amplifier; and a bias circuit that controls an operation point of the amplifier. The amplifier includes: a load resistor; a differential transistor pair electrically coupled to the load resistor; and a tail transistor electrically coupled to the differential transistor pair. The bias circuit includes: a voltage generator circuit that generates a reference voltage corresponding to a sum of a threshold voltage of a transistor in the differential transistor pair and a saturation drain voltage of the tail transistor; and a current generator circuit that generates a reference current that is proportional to a difference between a power supply voltage of the amplifier circuit and the reference voltage by using a reference resistor. The current generator circuit is electrically coupled to the amplifier such that a tail current that flows through the tail transistor is proportional to the reference current.

7. 发明申请

US20170054575A1 DECISION FEEDBACK EQUALIZER AND RECEIVER CIRCUIT 有权
标题翻译：决策反馈均衡器和接收器电路
公开(公告)号：US20170054575A1
公开(公告)日：2017-02-23
申请号：US15200626
申请日：2016-07-01
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai
IPC分类号： H04L25/03 , H04J11/00 , H04W72/04 , H04L12/26
CPC分类号： H04L25/03057 , H04L25/03006
摘要： A plurality of comparator circuits output results of comparing a pulse amplitude modulated input signal having four or more values with a plurality of first thresholds. A selection section decides a value of the input signal at certain timing by selecting one of the comparison results on the basis of a result of deciding a value of the input signal at previous timing. A threshold setting section generates the first thresholds from a plurality of third thresholds obtained by adding an offset value based on magnitude of inter-symbol interference corresponding to each value to one of second thresholds whose number is based on the number of values, on the basis of an average value of third thresholds greater than a second threshold or third thresholds smaller than the second threshold and an adjustment value based on the decision result and sets the first thresholds in the comparator circuits.
摘要翻译：多个比较器电路输出具有四个或更多个值的脉冲幅度调制输入信号与多个第一阈值的结果。选择部根据在上一次的时刻判定输入信号的值的结果，通过选择比较结果之一来决定某一定时的输入信号的值。阈值设定部分根据多个第三阈值生成第一阈值，该多个第三阈值是通过将基于每个值的码元间干扰的大小的偏移值与基于值的数量的第二阈值之一相加而获得的，具有大于第二阈值的第三阈值或小于第二阈值的第三阈值的平均值，以及基于判定结果的调整值，并且设置比较器电路中的第一阈值。

8. 发明授权

US09425777B2 Phase interpolator 有权
标题翻译：相位插值器
公开(公告)号：US09425777B2
公开(公告)日：2016-08-23
申请号：US14682377
申请日：2015-04-09
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai , Toshihiko Mori
IPC分类号： H04L25/02 , H03K5/13 , G06F1/02 , H04L27/18 , H04L7/00 , H04L27/00 , H03K5/00
CPC分类号： H03K5/13 , G06F1/022 , H03K2005/00052 , H04L7/0025 , H04L27/18 , H04L2027/0016
摘要： A phase interpolator has: a mixer configured to synthesize phases of a plurality of input cosine-wave or sine-wave signals whose phases are different from each other; and a bias generator configured to output a bias signal in accordance with a phase control signal to the mixer, and the mixer outputs a signal with a phase in accordance with the phase control signal.
摘要翻译：相位插值器具有：混频器，被配置为合成相位彼此不同的多个输入余弦波或正弦波信号的相位; 以及偏置发生器，被配置为根据相位控制信号向混频器输出偏置信号，并且混频器根据相位控制信号输出具有相位的信号。

9. 发明申请

US20210081783A1 INFORMATION PROCESSING APPARATUS, METHOD OF PROCESSING INFORMATION, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM FOR STORING INFORMATION PROCESSING PROGRAM 有权
公开(公告)号：US20210081783A1
公开(公告)日：2021-03-18
申请号：US16930356
申请日：2020-07-16
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai , Sosaku Moriki
IPC分类号： G06N3/08 , G06N3/04
摘要： An information processing apparatus includes: a memory configured to store program instructions to perform quantization on quantization target data; and a processor configured to execute the program instructions stored in the memory, the program instructions including: obtaining a distribution of appearance frequencies of a plurality of variable elements included in the quantization target data; and aligning a most significant bit position of a quantization position to a variable element smaller than a variable element of a maximum value among the plurality of variable elements based on the distribution of the appearance frequencies of the plurality of variable elements.

10. 发明申请

US20200334521A1 INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM 审中-公开
公开(公告)号：US20200334521A1
公开(公告)日：2020-10-22
申请号：US16840601
申请日：2020-04-06
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai
IPC分类号： G06N3/04 , G06N3/08 , G06K9/62
摘要： An information processing device that executes calculation of a neural network, includes a memory; and a processor coupled to the memory and the processor configured to: set a division position for quantization of a variable to be used for the calculation so that a quantization error based on a difference between the variable before the quantization and the variable after the quantization is reduced; and quantize the variable based on the division position set.

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