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1. 发明授权

US11632334B2 Communication apparatus and communication method 有权
公开(公告)号：US11632334B2
公开(公告)日：2023-04-18
申请号：US17468052
申请日：2021-09-07
申请人： FUJITSU LIMITED , RIKEN
发明人： Junichi Sugiyama , Katsuya Tsushita , Kentaro Sano , Tomohiro Ueno
IPC分类号： H04L47/263 , H04L47/11 , H04L49/90 , H04L47/31 , H04L47/25 , H04L47/6275
摘要： A first node and a second node transmit packets to a third node via a switch. The packets are buffered in a Tx buffer in the switch and then transmitted to the third node.
When the third node detects a sign of congestion at the Tx buffer based on the reception frequency of the packets, it is recognized, from transmitter addresses included in the received packets, that the nodes transmitting the packets to the third node are the first node and the second node, and a control packet for a transmission stop request is transmitted to the first node and the second node. On receiving the control packet for a transmission stop request, the first node stops transmission of only packets addressed to the third node. On receiving the control packet for a transmission stop request, the second node stops transmission of only packets addressed to the third node.

2. 发明申请

US20220086096A1 COMMUNICATION APPARATUS AND COMMUNICATION METHOD 有权
公开(公告)号：US20220086096A1
公开(公告)日：2022-03-17
申请号：US17468052
申请日：2021-09-07
申请人： FUJITSU LIMITED , RIKEN
发明人： Junichi Sugiyama , Katsuya Tsushita , Kentaro Sano , Tomohiro Ueno
IPC分类号： H04L12/825 , H04L12/801 , H04L12/865 , H04L12/833 , H04L12/861
摘要： A first node and a second node transmit packets to a third node via a switch. The packets are buffered in a Tx buffer in the switch and then transmitted to the third node.
When the third node detects a sign of congestion at the Tx buffer based on the reception frequency of the packets, it is recognized, from transmitter addresses included in the received packets, that the nodes transmitting the packets to the third node are the first node and the second node, and a control packet for a transmission stop request is transmitted to the first node and the second node. On receiving the control packet for a transmission stop request, the first node stops transmission of only packets addressed to the third node. On receiving the control packet for a transmission stop request, the second node stops transmission of only packets addressed to the third node.

3. 发明授权

US09183077B2 Data storage apparatus and method for storing data 有权
标题翻译：用于存储数据的数据存储装置和方法
公开(公告)号：US09183077B2
公开(公告)日：2015-11-10
申请号：US14143532
申请日：2013-12-30
申请人： FUJITSU LIMITED
发明人： Katsuya Tsushita
IPC分类号： G11C29/00 , G06F11/08 , G11C5/00 , G11C7/10
CPC分类号： G06F11/08 , G06F11/1048 , G11C5/005 , G11C7/1006
摘要： A data storage apparatus includes: a memory configured to store data; an input delay circuit configured to input a set of data of a plurality of bits into the memory at different timings between the plurality of bits by adding different delays to the plurality of bits in the set of data or by adding different delays to bits in bit groups obtained by grouping the plurality of bits in units of a consecutive bits; and an output delay circuit configured to obtain an original set of data, which is the set of data before the input delay circuit adds the different delays, by adding, to the plurality of bits in the set of data output from the memory, delays having a pattern opposite that of the delays added by the input delay circuit.
摘要翻译：数据存储装置包括：存储器，被配置为存储数据; 输入延迟电路，被配置为通过向数据集合中的多个比特添加不同的延迟，或者通过向比特中添加不同的延迟，将多个比特的一组数据输入到多个比特之间的不同定时通过以连续比特为单位对多个比特进行分组而获得的组; 以及输出延迟电路，被配置为通过将从存储器输出的数据组中的多个比特相加来获得作为输入延迟电路在不同延迟之前的数据集的原始数据集合，与由输入延迟电路相加的延迟相反的模式。

4. 发明申请

US20140289586A1 DATA STORAGE APPARATUS AND METHOD FOR STORING DATA 有权
标题翻译：数据存储装置和存储数据的方法
公开(公告)号：US20140289586A1
公开(公告)日：2014-09-25
申请号：US14143532
申请日：2013-12-30
申请人： FUJITSU LIMITED
发明人： Katsuya Tsushita
IPC分类号： G11C7/22 , G06F11/08
CPC分类号： G06F11/08 , G06F11/1048 , G11C5/005 , G11C7/1006
摘要： A data storage apparatus includes: a memory configured to store data; an input delay circuit configured to input a set of data of a plurality of bits into the memory at different timings between the plurality of bits by adding different delays to the plurality of bits in the set of data or by adding different delays to bits in bit groups obtained by grouping the plurality of bits in units of a consecutive bits; and an output delay circuit configured to obtain an original set of data, which is the set of data before the input delay circuit adds the different delays, by adding, to the plurality of bits in the set of data output from the memory, delays having a pattern opposite that of the delays added by the input delay circuit.
摘要翻译：数据存储装置包括：存储器，被配置为存储数据; 输入延迟电路，被配置为通过向数据集合中的多个比特添加不同的延迟，或者通过向比特中添加不同的延迟，将多个比特的一组数据输入到多个比特之间的不同定时通过以连续比特为单位对多个比特进行分组而获得的组; 以及输出延迟电路，被配置为通过将从存储器输出的数据组中的多个比特相加来获得作为输入延迟电路在不同延迟之前的数据集合的原始数据集合，与由输入延迟电路相加的延迟相反的模式。

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