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1. 发明授权

US08563336B2 Method for forming thin film resistor and terminal bond pad simultaneously 有权
标题翻译：同时形成薄膜电阻和端子焊盘的方法
公开(公告)号：US08563336B2
公开(公告)日：2013-10-22
申请号：US12342430
申请日：2008-12-23
申请人： Fen Chen , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , John C. Malinowski , Anthony K. Stamper
发明人： Fen Chen , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , John C. Malinowski , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： H01L28/20 , H01C7/006 , H01C17/075 , H01L21/7685 , H01L23/5228 , H01L23/53295 , H01L24/11 , H01L28/24 , H01L2224/0231 , H01L2224/02313 , H01L2224/0401 , H01L2224/04042 , H01L2224/05181 , H01L2224/05546 , H01L2224/05624 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2924/013
摘要： Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.
摘要翻译：公开了同时形成薄膜电阻器和端子接合焊盘的方法。一种方法包括在端子线上同时形成端子接合焊盘和在另外两条导线上形成薄膜电阻器。

2. 发明授权

US08497203B2 Semiconductor structures and methods of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US08497203B2
公开(公告)日：2013-07-30
申请号：US12856212
申请日：2010-08-13
申请人： Fen Chen , Zhong-Xiang He , Anthony K. Stamper
发明人： Fen Chen , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L21/4703
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76834 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures with airgaps and/or metal linings and methods of manufacture are provided. The method of forming an airgap in a wiring level includes forming adjacent wires in a dielectric layer. The method further includes forming a masking layer coincident with the adjacent wire and forming a first layer on the masking layer to reduce a size of an opening formed in the masking layer between the adjacent wires. The method further includes removing exposed portions of the first layer and the dielectric layer to form trenches between the adjacent wires. The method further includes forming an interlevel dielectric layer upon the dielectric layer, where the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires. A metal liner can also be formed in the trenches, prior to the formation of the airgap.
摘要翻译：提供具有气隙和/或金属衬里和制造方法的半导体结构。在布线层中形成气隙的方法包括在电介质层中形成相邻的布线。该方法还包括形成与相邻导线重合的掩模层，并在掩模层上形成第一层以减小形成在相邻导线之间的掩模层中的开口的尺寸。该方法还包括去除第一层和电介质层的暴露部分以在相邻导线之间形成沟槽。所述方法还包括在所述电介质层上形成层间电介质层，其中夹层所述层间电介质层以填充所述沟槽，使得在相邻导线之间形成气隙。在形成气隙之前，也可以在沟槽中形成金属衬垫。

3. 发明申请

US20120038037A1 SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE 有权
标题翻译：半导体结构和制造方法
公开(公告)号：US20120038037A1
公开(公告)日：2012-02-16
申请号：US12856212
申请日：2010-08-13
申请人： Fen Chen , Zhong-Xiang He , Anthony K. Stamper
发明人： Fen Chen , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76834 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures with airgaps and/or metal linings and methods of manufacture are provided. The method of forming an airgap in a wiring level includes forming adjacent wires in a dielectric layer. The method further includes forming a masking layer coincident with the adjacent wire and forming a first layer on the masking layer to reduce a size of an opening formed in the masking layer between the adjacent wires. The method further includes removing exposed portions of the first layer and the dielectric layer to form trenches between the adjacent wires. The method further includes forming an interlevel dielectric layer upon the dielectric layer, where the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires. A metal liner can also be formed in the trenches, prior to the formation of the airgap.
摘要翻译：提供具有气隙和/或金属衬里和制造方法的半导体结构。在布线层中形成气隙的方法包括在电介质层中形成相邻的布线。该方法还包括形成与相邻导线重合的掩模层，并在掩模层上形成第一层以减小形成在相邻导线之间的掩模层中的开口的尺寸。该方法还包括去除第一层和电介质层的暴露部分以在相邻导线之间形成沟槽。所述方法还包括在所述电介质层上形成层间电介质层，其中夹层所述层间电介质层以填充所述沟槽，使得在相邻导线之间形成气隙。在形成气隙之前，也可以在沟槽中形成金属衬垫。

4. 发明授权

US08237463B1 Method for managing circuit reliability 失效
标题翻译：管理电路可靠性的方法
公开(公告)号：US08237463B1
公开(公告)日：2012-08-07
申请号：US13034758
申请日：2011-02-25
申请人： Fen Chen , Kai D. Feng , Zhong-Xiang He
发明人： Fen Chen , Kai D. Feng , Zhong-Xiang He
IPC分类号： H03K19/003
CPC分类号： H03K19/00307
摘要： Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.
摘要翻译：管理包括多个重复部件的电路的可靠性，其中小于所有组件在电路操作期间的任何时间处于活动状态，其中可靠性由电路通过第一组组件来管理，该组件包括预定义的组件数量; 根据电路可靠性协议选择不改变电路性能的第二组组件，包括激活非活动组件和去激活第一组组件的活动组件; 并通过电路与第二组元件一起操作。

5. 发明申请

US20120218030A1 METHOD FOR MANAGING CIRCUIT RELIABILITY 失效
标题翻译：管理电路可靠性的方法
公开(公告)号：US20120218030A1
公开(公告)日：2012-08-30
申请号：US13034758
申请日：2011-02-25
申请人： Fen Chen , Kai D. Feng , Zhong-Xiang He
发明人： Fen Chen , Kai D. Feng , Zhong-Xiang He
IPC分类号： H03K19/003
CPC分类号： H03K19/00307
摘要： Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.
摘要翻译：管理包括多个重复部件的电路的可靠性，其中小于所有组件在电路操作期间的任何时间处于活动状态，其中可靠性由电路通过第一组组件来管理，该组件包括预定义的组件数量; 根据电路可靠性协议选择不改变电路性能的第二组组件，包括激活非活动组件和去激活第一组组件的活动组件; 并通过电路与第二组元件一起操作。

6. 发明申请

US20110018575A1 METHOD AND SYSTEM FOR ASSESSING RELIABILITY OF INTEGRATED CIRCUIT 有权
标题翻译：用于评估集成电路可靠性的方法和系统
公开(公告)号：US20110018575A1
公开(公告)日：2011-01-27
申请号：US12508111
申请日：2009-07-23
申请人： Fen Chen , Kai D. Feng , Zhong-Xiang He
发明人： Fen Chen , Kai D. Feng , Zhong-Xiang He
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R31/2621 , G01R31/2855 , G01R31/2894
摘要： The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC).
摘要翻译：本发明提供一种方法。该方法包括在第一操作条件下操作多个场效应晶体管（FET）; 短时间内反转多个FET中的至少一个的操作方向; 在短时间内测量所述多个FET中的一个的第二操作条件; 计算第二操作条件和参考操作条件之间的差; 以及基于所述第二参考操作条件和所述参考操作条件之间的差异提供可靠性指示器，其中所述多个FET用于单个集成电路（IC）。

7. 发明授权

US08362794B2 Method and system for assessing reliability of integrated circuit 有权
标题翻译：评估集成电路可靠性的方法和系统
公开(公告)号：US08362794B2
公开(公告)日：2013-01-29
申请号：US12508111
申请日：2009-07-23
申请人： Fen Chen , Kai D Feng , Zhong-Xiang He
发明人： Fen Chen , Kai D Feng , Zhong-Xiang He
IPC分类号： G01R31/02
CPC分类号： G01R31/2621 , G01R31/2855 , G01R31/2894
摘要： The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC).
摘要翻译：本发明提供一种方法。该方法包括在第一操作条件下操作多个场效应晶体管（FET）; 短时间内反转多个FET中的至少一个的操作方向; 在短时间内测量所述多个FET中的一个的第二操作条件; 计算第二操作条件和参考操作条件之间的差; 以及基于所述第二参考操作条件和所述参考操作条件之间的差异提供可靠性指示器，其中所述多个FET用于单个集成电路（IC）。

8. 发明授权

US08569888B2 Wiring structure and method of forming the structure 有权
标题翻译：布线结构及形成方法
公开(公告)号：US08569888B2
公开(公告)日：2013-10-29
申请号：US13114079
申请日：2011-05-24
申请人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76843 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
摘要翻译：公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。较厚的上部位于布线结构和相邻电介质材料之间的接合处。较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

9. 发明申请

US20120299188A1 WIRING STRUCTURE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：导线结构及形成结构的方法
公开(公告)号：US20120299188A1
公开(公告)日：2012-11-29
申请号：US13114079
申请日：2011-05-24
申请人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/76843 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
摘要翻译：公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。较厚的上部位于布线结构和相邻电介质材料之间的接合处。较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

10. 发明授权

US08917104B2 Analyzing EM performance during IC manufacturing 有权
标题翻译：分析IC制造过程中的EM性能
公开(公告)号：US08917104B2
公开(公告)日：2014-12-23
申请号：US13222306
申请日：2011-08-31
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187 , G01R31/28
CPC分类号： G01R31/2858
摘要： A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.
摘要翻译：用于监测电迁移（EM）性能的测试结构，系统和方法。描述了包括测试结构阵列的系统，其中每个测试结构包括：具有四点电阻测量的EM电阻器，其中第一和第二端子提供电流输入，第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量，其栅极由选择开关控制，并且其漏极用于在第三和第四端子处提供电压测量。还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。

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