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1. 发明授权

US08040907B2 Switching method 有权
标题翻译：切换方式
公开(公告)号：US08040907B2
公开(公告)日：2011-10-18
申请号：US12252934
申请日：2008-10-16
申请人： Finbar Naven , Paul Howarth
发明人： Finbar Naven , Paul Howarth
IPC分类号： H04L12/56
CPC分类号： H04L47/527 , H04L47/50 , H04L47/52 , H04L47/58 , H04L47/60 , H04L47/6205 , H04L49/254 , H04L49/3018 , H04L49/50
摘要： A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through the ingress ports and to forward received data packets to respective ones of the egress ports. The switching device further comprises an ingress module for each of the ingress ports, each ingress module being arranged to receive data packets from a respective single one of the ingress ports and to store the received data packets in one of a plurality of data structures provided by the ingress module, each ingress module being further configured to select a data packet from one of the plurality of data structures, and to request permission to transmit the selected data packet to an egress port. The switching device also comprises at least one egress module arranged to receive a plurality of requests for permission to transmit data packets through a particular egress port, the request being generated by the plurality of ingress modules, and to select one of the plurality of requests.
摘要翻译：一种交换设备，包括多个入口和多个出口。交换设备被布置成通过入口端口接收数据分组，并将接收到的数据分组转发到相应的出口端口。交换设备还包括用于每个入口端口的入口模块，每个入口模块被布置成从相应的单个入口端口接收数据分组，并将接收到的数据分组存储在由多个数据结构提供的多个数据结构之一所述入口模块，每个入口模块还被配置为从所述多个数据结构之一中选择数据分组，并且请求允许将所选择的数据分组发送到出口端口。所述交换设备还包括至少一个出口模块，所述至少一个出口模块被布置为接收多个请求以允许通过特定出口端口发送数据分组，所述请求由所述多个入口模块生成，并且选择所述多个请求之一。

2. 发明申请

US20100002716A1 SWITCHING METHOD 有权
标题翻译：切换方式
公开(公告)号：US20100002716A1
公开(公告)日：2010-01-07
申请号：US12252934
申请日：2008-10-16
申请人： Finbar Naven , Paul Howarth
发明人： Finbar Naven , Paul Howarth
IPC分类号： H04L12/56
CPC分类号： H04L47/527 , H04L47/50 , H04L47/52 , H04L47/58 , H04L47/60 , H04L47/6205 , H04L49/254 , H04L49/3018 , H04L49/50
摘要： A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through said ingress ports and to forward received data packets to respective ones of said egress ports. The switching device further comprises an ingress module for each of said ingress ports, each ingress module being arranged to receive data packets from a respective single one of said ingress ports and to store the received data packets in one of a plurality of data structures provided by the ingress module, each ingress module being further configured to select a data packet from one of said plurality of data structures, and to request permission to transmit the selected data packet to an egress port. The switching device also comprises at least one egress module arranged to receive a plurality of requests for permission to transmit data packets through a particular egress port, the request being generated by the plurality of ingress modules, and to select one of said plurality of requests.
摘要翻译：一种交换设备，包括多个入口和多个出口。交换设备被配置为通过所述入口端口接收数据分组，并将接收到的数据分组转发到相应的所述出口端口。交换设备还包括用于每个所述入口端口的入口模块，每个入口模块被布置成从相应的一个所述入口端口接收数据分组，并将所接收的数据分组存储在由多个数据结构提供的多个数据结构之一所述入口模块，每个入口模块还被配置为从所述多个数据结构之一中选择数据分组，并请求允许将所选择的数据分组发送到出口端口。交换设备还包括至少一个出口模块，其布置成接收多个请求以允许通过特定出口端口发送数据分组，所述请求由多个入口模块生成，并且选择所述多个请求之一。

3. 发明授权

US08085800B2 Queuing method 有权
标题翻译：排队方式
公开(公告)号：US08085800B2
公开(公告)日：2011-12-27
申请号：US12211192
申请日：2008-09-16
申请人： Finbar Naven , Stephen John Marshall
发明人： Finbar Naven , Stephen John Marshall
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L47/50 , H04L47/52 , H04L47/623 , H04L49/901
摘要： A method of queuing data packets, said data packets comprising data packets of a first packet type and data packets of a second packet type. The method comprises grouping received packets of said first and second packet types into an ordered series of groups, each group comprising at least one packet, maintaining a group counter indicating the number of groups at the beginning of the series of groups comprising only packets of the second packet type, and transmitting a packet. A packet of the second packet type is available for transmission if but only if the group counter is indicative that the number of groups at the beginning of the series of groups comprising only packets of the second packet type is greater than zero.
摘要翻译：排队数据分组的方法，所述数据分组包括第一分组类型的数据分组和第二分组类型的数据分组。该方法包括将接收到的所述第一和第二分组类型的分组分组成有序的一组分组，每组包括至少一个分组，维持组计数器，该组计数器指示在仅包括分组的分组的一系列组的开始处的组数第二分组类型，并发送分组。第二分组类型的分组可用于传输，但是仅当组计数器指示仅包括第二分组类型的分组的一系列组的开始处的组的数量大于零时。

4. 发明申请

US20090086747A1 Queuing Method 有权
标题翻译：排队方法
公开(公告)号：US20090086747A1
公开(公告)日：2009-04-02
申请号：US12211192
申请日：2008-09-16
申请人： Finbar Naven , Stephen John Marshall
发明人： Finbar Naven , Stephen John Marshall
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L47/50 , H04L47/52 , H04L47/623 , H04L49/901
摘要： A method of queuing data packets, said data packets comprising data packets of a first packet type and data packets of a second packet type. The method comprises grouping received packets of said first and second packet types into an ordered series of groups, each group comprising at least one packet, maintaining a group counter indicating the number of groups at the beginning of the series of groups comprising only packets of the second packet type, and transmitting a packet. A packet of the second packet type is available for transmission if but only if the group counter is indicative that the number of groups at the beginning of the series of groups comprising only packets of the second packet type is greater than zero.
摘要翻译：排队数据分组的方法，所述数据分组包括第一分组类型的数据分组和第二分组类型的数据分组。该方法包括将接收到的所述第一和第二分组类型的分组分组成有序的一组分组，每组包括至少一个分组，维持组计数器，该组计数器指示在仅包括分组的分组的一系列组的开始处的组数第二分组类型，并发送分组。第二分组类型的分组可用于传输，但是仅当组计数器指示仅包括第二分组类型的分组的一系列组的开始处的组的数量大于零时。

5. 发明授权

US06810043B1 Scheduling circuitry and methods 有权
标题翻译：调度电路和方法
公开(公告)号：US06810043B1
公开(公告)日：2004-10-26
申请号：US09304843
申请日：1999-05-05
申请人： Finbar Naven , Paul Barnes , Simon Timothy Smith
发明人： Finbar Naven , Paul Barnes , Simon Timothy Smith
IPC分类号： H04L1256
CPC分类号： H04L12/5602 , H04L2012/5679 , H04L2012/5681 , H04Q11/0478
摘要： Scheduling circuitry, for use for example in an ATM network unit to schedule cell transmissions, includes a master calendar (1) for holding entries corresponding respectively to events (cell transmissions) that are to occur within a preselected master-calendar scheduling range (SR), and a slave calendar (12) for holding entries corresponding respectively to events that are to occur beyond that scheduling range. When an event is to be scheduled, calendar control circuitry (24) makes an entry corresponding thereto in the slave calendar (12) if the interval between a current time and a desired scheduling time for the event exceeds said scheduling range. The entry in the slave calendar includes timing information representing the desired scheduling time. The calendar control circuitry monitors the entries in the slave calendar (12) and causes an entry therein whose corresponding event becomes within the scheduling range to be transferred to the master calendar (1). Such scheduling circuitry can deal effectively with events that are to be scheduled at widely disparate intervals (very short and very long) without requiring the calendars to be large and without complicated processing of the calendar entries.
摘要翻译：用于例如在ATM网络单元中调度小区传输的调度电路包括主日历（1），用于保存分别对应于在预先选择的主日历调度范围（SR）内发生的事件（小区传输）的条目，，以及从日历（12），用于保存分别对应于超出该调度范围的事件的条目。如果要安排事件，则如果事件的当前时间和期望调度时间之间的间隔超过所述调度范围，则日历控制电路（24）在从日历（12）中进行与其对应的条目。从日历中的条目包括表示所需调度时间的定时信息。日历控制电路监视从属日历（12）中的条目，并使其中对应事件变成调度范围内的条目传送到主日历（1）。这样的调度电路可以有效地处理将要发生的事件安排在不同的时间间隔（非常短和非常长），而不需要日历大，并且没有日历条目的复杂处理。

6. 发明授权

US4730316A Digital integrated circuits 失效
标题翻译：数字集成电路
公开(公告)号：US4730316A
公开(公告)日：1988-03-08
申请号：US882949
申请日：1986-07-07
申请人： Peter L. L. Desyllas , Finbar Naven
发明人： Peter L. L. Desyllas , Finbar Naven
IPC分类号： G01R31/3185 , G06F11/267 , G01R31/28
CPC分类号： G01R31/318536 , G01R31/318555 , G06F11/2236
摘要： A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes: USER, HOLD, SHIFT and SELF-TEST modes. These modes are controlled by shifting a control function into a control shift register. When the shifting of the control shift register stops, a command is automatically loaded from the control shift register (or another source) into a command register, which controls the serial shift paths. The provision of a separate command register allows a new control function to be shifted into the control shift register while a preceding command is still active in the command register.
摘要翻译：描述了一种数字集成电路，其中内部寄存器被组织成多个串行移位路径以便于测试。每个路径都有多种模式：USER，HOLD，SHIFT和SELF-TEST模式。这些模式通过将控制功能转换为控制移位寄存器来控制。当控制移位寄存器的移位停止时，命令从控制移位寄存器（或另一个源）自动加载到控制串行移位路径的命令寄存器中。提供单独的命令寄存器允许在控制移位寄存器中移动新的控制功能，同时前一个命令在命令寄存器中仍然有效。

7. 发明申请

US20120155520A1 DATA SWITCH 有权
标题翻译：数据开关
公开(公告)号：US20120155520A1
公开(公告)日：2012-06-21
申请号：US13408634
申请日：2012-02-29
申请人： Finbar Naven , John Roger Drewry
发明人： Finbar Naven , John Roger Drewry
IPC分类号： H04B1/38
CPC分类号： H04J3/0685 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/901 , H04L2012/5674
摘要： A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.
摘要翻译：一种用于集成电路的数据开关，包括用于从具有预定扩频链路时钟频率特性的独立调制扩频时钟（SSC）使能源接收输入数据分组的至少一个链路，以及用于在通过之后发送数据分组的至少一个输出通过开关，开关进一步包括至少一个具有链路侧和核心侧的接收缓冲器，用于从链路，至少一个发射缓冲器和核心时钟接收SSC调制的输入数据分组，其中核心时钟在给定频率在单独的振荡精度确定的预定误差极限之间并且不是SSC使能的，核心时钟频率被设置在至少与最高链路时钟频率一样高的水平，使得接收缓冲器不能从其链路侧更快地被填充比它的核心方面可以排空。

8. 发明申请

US20100014428A1 SWITCHING DEVICE 有权
标题翻译：切换设备
公开(公告)号：US20100014428A1
公开(公告)日：2010-01-21
申请号：US12252882
申请日：2008-10-16
申请人： Finbar Naven , Stephen John Marshall
发明人： Finbar Naven , Stephen John Marshall
IPC分类号： H04L12/26 , H04L12/56
CPC分类号： H04L49/3045 , H04L49/3018 , H04L49/508
摘要： A switching device comprising at least one ingress port and at least one egress port. The switching device is arranged to receive data packets through said at least one ingress port and to forward received data packets to respective ones of said at least one egress port. The switching device further comprises a primary buffer arranged to store data packets received via at least one of said at least one ingress ports and a secondary buffer associated with the primary buffer. The switching device is adapted to select a data packet from said primary buffer and if but only if said secondary buffer satisfies a least one first predetermined criterion, transfer said selected data packet to said secondary buffer.
摘要翻译：一种交换设备，包括至少一个入口和至少一个出口。交换设备被布置成通过所述至少一个入口接收数据分组，并将接收的数据分组转发到所述至少一个出口端口中的相应的一个出口端口。交换设备还包括主缓冲器，其被配置为存储经由所述至少一个入口端口中的至少一个接收的数据分组和与主缓冲器相关联的次缓冲器。交换设备适于从所述主缓冲器中选择数据分组，并且如果但是仅当所述辅助缓冲器满足至少一个第一预定标准时，则将所述选择的数据分组传送到所述辅助缓冲器。

9. 发明授权

US06556506B2 Memory access methods and devices for use with random access memories 有权
标题翻译：用于随机存取存储器的存储器访问方法和设备
公开(公告)号：US06556506B2
公开(公告)日：2003-04-29
申请号：US10043138
申请日：2002-01-14
申请人： Finbar Naven
发明人： Finbar Naven
IPC分类号： G11C800
CPC分类号： G06F13/1647 , G06F12/0607 , G11C7/1039 , G11C7/1042 , G11C8/12 , G11C11/409
摘要： In a memory access method used with a synchronous dynamic random access memory (SDRAM) having first and second banks, each information item is allocated respective first and second storage locations in the memory. The first and second storage locations are in the first and second banks (Bank 0, Bank 1) respectively. When, in the same time slot, it is required to write a first such information item (W) in the memory and to read a second such information item (R) from the memory, it is firstly determined which of the first and second banks currently holds the second information item (R). The first information item (W) is written in the first storage location allocated thereto if the determined bank is the second bank and is written in the second storage location allocated thereto if the determined bank is the first bank. The second information item (R) is read from the determined bank after the first information is written. As a result, the write and read operations can be interleaved, providing increasing throughput as is desirable in, for example, pipelined memory access systems. Other SDRAM access method and devices for improving throughput also apply.
摘要翻译：在与具有第一和第二存储体的同步动态随机存取存储器（SDRAM）一起使用的存储器访问方法中，每个信息项目被分配在存储器中的相应的第一和第二存储位置。第一和第二存储单元分别位于第一和第二组（组0，组1）中。当在相同的时隙中，需要在存储器中写入第一个这样的信息项（W）并且从存储器读取第二个这样的信息项（R）时，首先确定第一和第二组中的哪一个当前持有第二信息项目（R）。如果确定的银行是第二银行，则第一信息项（W）被写入分配给它的第一存储位置，并且如果确定的银行是第一存储体，则被写入分配给它的第二存储位置。在写入第一信息之后，从确定的存储体读取第二信息项目（R）。结果，写入和读取操作可以被交织，从而提供如在流水线存储器访问系统中所希望的增加的吞吐量。其他用于提高吞吐量的SDRAM访问方法和设备也适用。

10. 发明授权

US5936956A Data receiving devices 失效
标题翻译：数据接收设备
公开(公告)号：US5936956A
公开(公告)日：1999-08-10
申请号：US688093
申请日：1996-07-29
申请人： Finbar Naven
发明人： Finbar Naven
IPC分类号： H04Q3/00 , G06F13/38 , H04L12/56 , H04Q11/04 , G06F13/00 , G06F7/00
CPC分类号： H04Q11/0478 , G06F13/387 , H04L2012/5615 , H04L2012/5616 , H04L2012/5651 , H04L2012/5681
摘要： A data receiving device, for receiving data from an ATM network, has a data storage circuit (38) for allocating preselected virtual channels of the network with respect to corresponding storage regions (5r) in a local memory (5) connected with the device. The storage regions are in the form of linked lists. When data items belonging to the different preselected virtual channels are received in succession by the device, the data storage circuit (38) stores those items in the storage regions that correspond respectively to the items' virtual channels. As a result, transfer of the received data items from the local memory (5) to a further connected apparatus (7) connected with the device, is performed in a different channel order form that in which those items were received by the device from the network. The latter transfer may be performed by the connected further apparatus or by a data transfer circuit (40) of the device.
摘要翻译：一种用于从ATM网络接收数据的数据接收装置，具有数据存储电路（38），用于相对于与设备连接的本地存储器（5）中的对应存储区域（5r）分配网络的预选虚拟通道。存储区域是链表的形式。当属于不同预选虚拟频道的数据项被设备连续接收时，数据存储电路（38）将这些项目存储在分别对应于项目的虚拟通道的存储区域中。结果，将接收到的数据项从本地存储器（5）传送到与设备连接的另外连接的设备（7），以不同的通道顺序形式执行，其中这些项目被设备从网络。后一种传输可以由连接的另外的设备或设备的数据传输电路（40）执行。

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