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1. 发明授权

US07120771B2 Secure mode for processors supporting MMU 有权
标题翻译：支持MMU的处理器的安全模式
公开(公告)号：US07120771B2
公开(公告)日：2006-10-10
申请号：US10256596
申请日：2002-09-27
申请人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
发明人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
IPC分类号： G06F12/00
CPC分类号： G06F21/556 , G06F9/30047 , G06F9/3802 , G06F9/468 , G06F12/1491 , G06F21/51 , G06F21/52 , G06F21/74 , G06F21/82 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , G06F2221/2143 , G06F2221/2149 , G06F2221/2153
摘要： A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
摘要翻译：在包括处理器核心，指令和数据高速缓冲存储器，写入缓冲器和写入缓冲器的处理器系统中，数字系统被提供有以非侵入式方式构建的安全模式（3级的特权级别）内存管理单元。因此，在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。特别是操作系统不受信任，所有本地应用程序都不被信任。提供了一种安全执行模式，当启用存储器管理单元（MMU）时允许虚拟寻址。安全执行模式允许指令和数据高速缓存启用。提供了一种安全执行模式，允许所有系统中断被隐藏。通过唯一的入口点输入安全模式。安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。监视一个特定的条目条目，这些条目占用缓存，写入缓冲区和MMU被启用。激活序列代码的结构用于缓存，写入缓冲区和MMU被使能。退出序列代码的结构用于缓存，写入缓冲区和MMU被启用。提供了一种具体的方法来管理通用中断下安全模式的安全退出，并允许从中断通过入口点和激活顺序返回，并适当恢复安全执行。提供了以安全模式管理MMU的特定方式，并在安全和非安全环境之间提供数据交换。

2. 发明授权

US07890753B2 Secure mode for processors supporting MMU and interrupts 有权
标题翻译：支持MMU和中断的处理器的安全模式
公开(公告)号：US07890753B2
公开(公告)日：2011-02-15
申请号：US10256642
申请日：2002-09-27
申请人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
发明人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
IPC分类号： H04L29/06
CPC分类号： G06F21/556 , G06F9/30047 , G06F9/3802 , G06F9/468 , G06F12/1491 , G06F21/51 , G06F21/52 , G06F21/74 , G06F21/82 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , G06F2221/2143 , G06F2221/2149 , G06F2221/2153
摘要： A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
摘要翻译：在包括处理器核心，指令和数据高速缓存，写入缓冲器和存储器管理单元的处理器系统上，数字系统被提供有以非侵入式方式内置的安全模式（第三级特权）。因此，在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。特别是操作系统不受信任，所有本地应用程序都不被信任。提供了一种安全执行模式，当启用存储器管理单元（MMU）时允许虚拟寻址。安全执行模式允许指令和数据高速缓存启用。提供了一种安全执行模式，允许所有系统中断被隐藏。通过唯一的入口点输入安全模式。安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。监视一个特定的条目条目，这些条目占用缓存，写入缓冲区和MMU被启用。激活序列代码的结构用于缓存，写入缓冲区和MMU被使能。退出序列代码的结构用于缓存，写入缓冲区和MMU被启用。提供了一种具体的方法来管理通用中断下安全模式的安全退出，并允许从中断通过入口点和激活顺序返回，并适当恢复安全执行。提供了以安全模式管理MMU的特定方式，并在安全和非安全环境之间提供数据交换。

3. 发明授权

US07237081B2 Secure mode for processors supporting interrupts 有权
标题翻译：支持中断的处理器的安全模式
公开(公告)号：US07237081B2
公开(公告)日：2007-06-26
申请号：US10256523
申请日：2002-09-27
申请人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
发明人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
IPC分类号： G06F12/14 , G06F11/30 , G06F12/00 , H04L9/32 , H04L9/00
CPC分类号： G06F21/556 , G06F9/30047 , G06F9/3802 , G06F9/468 , G06F12/1491 , G06F21/51 , G06F21/52 , G06F21/74 , G06F21/82 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , G06F2221/2143 , G06F2221/2149 , G06F2221/2153
摘要： A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
摘要翻译：在包括处理器核心，指令和数据高速缓冲存储器，写入缓冲器和写入缓冲器的处理器系统中，数字系统被提供有以非侵入式方式构建的安全模式（3级的特权级别）内存管理单元。因此，在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。特别是操作系统不受信任，所有本地应用程序都不被信任。提供了一种安全执行模式，当启用存储器管理单元（MMU）时允许虚拟寻址。安全执行模式允许指令和数据高速缓存启用。提供了一种安全执行模式，允许所有系统中断被隐藏。通过唯一的入口点输入安全模式。安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。监视一个特定的条目条目，这些条目占用缓存，写入缓冲区和MMU被启用。激活序列代码的结构用于缓存，写入缓冲区和MMU被使能。退出序列代码的结构用于缓存，写入缓冲区和MMU被启用。提供了一种具体的方法来管理通用中断下安全模式的安全退出，并允许从中断通过入口点和激活顺序返回，并适当恢复安全执行。提供了以安全模式管理MMU的特定方式，并在安全和非安全环境之间提供数据交换。

4. 发明申请

US20120005471A1 BOOTING AN INTEGRATED CIRCUIT 有权
标题翻译：组装集成电路
公开(公告)号：US20120005471A1
公开(公告)日：2012-01-05
申请号：US13228170
申请日：2011-09-08
申请人： Peter Cumming , Stephen Felix
发明人： Peter Cumming , Stephen Felix
IPC分类号： G06F9/00
CPC分类号： G06F9/441
摘要： An integrated circuit is disclosed herein. In one embodiment, the integrated circuit includes: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.
摘要翻译：本文公开了集成电路。在一个实施例中，集成电路包括：处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到处理器的永久写入的存储器，所述存储器具有多个区域，每个区域存储用于引导处理器的一个或多个相应的引导属性。处理器被编程为根据经由一个或多个外部引脚接收的指示来选择一个区域，以从所选择的区域检索一个或多个相应的引导属性，并使用一个或多个检索到的引导属性进行引导。

5. 发明授权

US08024557B2 Booting an integrated circuit 有权
标题翻译：引导集成电路
公开(公告)号：US08024557B2
公开(公告)日：2011-09-20
申请号：US12127131
申请日：2008-05-27
申请人： Peter Cumming , Stephen Felix
发明人： Peter Cumming , Stephen Felix
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177
CPC分类号： G06F9/441
摘要： An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.
摘要翻译：一种集成电路，包括：处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到所述处理器的永久写入的存储器，所述存储器具有多个区域，每个区域存储用于引导所述处理器的一个或多个相应的引导属性。处理器被编程为根据经由一个或多个外部引脚接收到的指示来选择一个区域，以从所选择的区域检索一个或多个相应的引导属性，并使用一个或多个检索到的引导属性进行引导。

6. 发明授权

US07996581B2 DMA engine 有权
标题翻译： DMA引擎
公开(公告)号：US07996581B2
公开(公告)日：2011-08-09
申请号：US12466038
申请日：2009-05-14
申请人： Andrew Bond , Peter Cumming , Colman Hegarty
发明人： Andrew Bond , Peter Cumming , Colman Hegarty
IPC分类号： G06F13/28
CPC分类号： G06F13/30
摘要： A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch while one or more others perform a transfer.
摘要翻译：一种用于传输数据的电路和相应的方法。该电路包括：CPU; 多个可寻址装置; 以及耦合到CPU和那些设备的DMA引擎，DMA引擎包括多个DMA上下文，每个DMA上下文具有用于取出由CPU指示的DMA描述符的读取电路和用于基于一个获取的描述符。 DMA引擎还包括切换装置，其可操作以控制一组上下文在获取和执行传送之间的互补序列中交替，使得当一个或多个其他执行传送时，组提取中的一个或多个上下文交替。

7. 发明授权

US5873115A Cache memory 失效
标题翻译：高速缓存存储器
公开(公告)号：US5873115A
公开(公告)日：1999-02-16
申请号：US735863
申请日：1996-10-23
申请人： Peter Cumming , Richard Grisenthwaite
发明人： Peter Cumming , Richard Grisenthwaite
IPC分类号： G06F9/38 , G06F12/00
CPC分类号： G06F9/3806
摘要： A cache memory has a plurality of cache partitions each having a CAM array, a data RAM and output control circuitry which determines a different priority for each cache partition and permits a cache hit output only from one partition which has the highest priority with a cache hit.
摘要翻译：高速缓存存储器具有多个高速缓存分区，每个高速缓存分区具有CAM阵列，数据RAM和输出控制电路，其确定每个高速缓存分区的不同优先级，并允许仅从具有最高优先级的一个分区的高速缓存命中输出与高速缓存命中。

8. 发明授权

US08589602B2 Data transfer engine with delay circuitry for blocking transfers 有权
标题翻译：具有阻塞传输延迟电路的数据传输引擎
公开(公告)号：US08589602B2
公开(公告)日：2013-11-19
申请号：US13057679
申请日：2009-05-26
申请人： Andrew Bond , Peter Cumming , Fabienne Hegarty
发明人： Andrew Bond , Peter Cumming , Coleman Hegarty
IPC分类号： G06F13/28 , G06F3/00
CPC分类号： G06F13/28
摘要： A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors.
摘要翻译：一种电路，包括：执行单元; 多个可寻址装置; 以及耦合到所述执行单元和所述设备的数据传输引擎，用于在所述执行单元的控制下获取多个描述符，并且基于每个所述获取的描述符，以执行数据从相应的第一到第第二个设备。 DMA引擎包括延迟电路，其可操作以在延迟时段期间从更早的传输中阻止任何稍后的传输，其涉及与早期传输相同的设备中的至少一个，延迟电路被布置为控制阻塞依赖于在其中一个描述符中接收到的指示。

9. 发明授权

US08341451B2 Clock configuration 有权
标题翻译：时钟配置
公开(公告)号：US08341451B2
公开(公告)日：2012-12-25
申请号：US12428728
申请日：2009-04-23
申请人： Jon Mangnall , Peter Cumming
发明人： Jon Mangnall , Peter Cumming
IPC分类号： G06F1/00 , G06F9/00
CPC分类号： G06F1/04 , G06F9/4401
摘要： A circuit and method for determining the frequency of a first oscillating reference signal generated by a first reference oscillator. The circuit comprises: a second reference oscillator arranged to generate a second oscillating reference signal having a known frequency, a boot memory storing boot code comprising clock configuration code, and a processor coupled to the boot memory and the second reference oscillator. The processor is arranged to execute the boot code from the boot memory upon booting, wherein when executed the clock configuration code operates the processor to determine the frequency of the first reference signal by reference to the second reference signal.
摘要翻译：一种用于确定由第一参考振荡器产生的第一振荡参考信号的频率的电路和方法。该电路包括：第二参考振荡器，被配置为产生具有已知频率的第二振荡参考信号，引导存储器存储包括时钟配置码的引导代码，以及耦合到引导存储器和第二参考振荡器的处理器。处理器被布置为在引导时从引导存储器执行引导代码，其中当执行时，时钟配置代码操作处理器，以参考第二参考信号来确定第一参考信号的频率。

10. 发明申请

US20110191507A1 DMA ENGINE 有权
标题翻译： DMA引擎
公开(公告)号：US20110191507A1
公开(公告)日：2011-08-04
申请号：US13057679
申请日：2009-05-26
申请人： Andrew Bond , Peter Cumming , Colman Hegarty , Fabienne Hegarty
发明人： Andrew Bond , Peter Cumming , Colman Hegarty , Fabienne Hegarty
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors.
摘要翻译：一种电路，包括：执行单元; 多个可寻址装置; 以及耦合到所述执行单元和所述设备的数据传输引擎，用于在所述执行单元的控制下获取多个描述符，并且基于每个所述获取的描述符，以执行数据从相应的第一到第第二个设备。 DMA引擎包括延迟电路，其可操作以在延迟时段期间从更早的传输中阻止任何稍后的传输，其涉及与早期传输相同的设备中的至少一个，延迟电路被布置为控制阻塞依赖于在其中一个描述符中接收到的指示。

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