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    • 5. 发明授权
    • Secure mode for processors supporting MMU and interrupts
    • 支持MMU和中断的处理器的安全模式
    • US07890753B2
    • 2011-02-15
    • US10256642
    • 2002-09-27
    • Franck DahanChristian RousselAlain ChateauPeter Cumming
    • Franck DahanChristian RousselAlain ChateauPeter Cumming
    • H04L29/06
    • G06F21/556G06F9/30047G06F9/3802G06F9/468G06F12/1491G06F21/51G06F21/52G06F21/74G06F21/82G06F2221/2101G06F2221/2105G06F2221/2141G06F2221/2143G06F2221/2149G06F2221/2153
    • A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
    • 在包括处理器核心,指令和数据高速缓存,写入缓冲器和存储器管理单元的处理器系统上,数字系统被提供有以非侵入式方式内置的安全模式(第三级特权)。 因此,在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。 特别是操作系统不受信任,所有本地应用程序都不被信任。 提供了一种安全执行模式,当启用存储器管理单元(MMU)时允许虚拟寻址。 安全执行模式允许指令和数据高速缓存启用。 提供了一种安全执行模式,允许所有系统中断被隐藏。 通过唯一的入口点输入安全模式。 安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。 监视一个特定的条目条目,这些条目占用缓存,写入缓冲区和MMU被启用。 激活序列代码的结构用于缓存,写入缓冲区和MMU被使能。 退出序列代码的结构用于缓存,写入缓冲区和MMU被启用。 提供了一种具体的方法来管理通用中断下安全模式的安全退出,并允许从中断通过入口点和激活顺序返回,并适当恢复安全执行。 提供了以安全模式管理MMU的特定方式,并在安全和非安全环境之间提供数据交换。
    • 6. 发明授权
    • Secure mode for processors supporting interrupts
    • 支持中断的处理器的安全模式
    • US07237081B2
    • 2007-06-26
    • US10256523
    • 2002-09-27
    • Franck DahanChristian RousselAlain ChateauPeter Cumming
    • Franck DahanChristian RousselAlain ChateauPeter Cumming
    • G06F12/14G06F11/30G06F12/00H04L9/32H04L9/00
    • G06F21/556G06F9/30047G06F9/3802G06F9/468G06F12/1491G06F21/51G06F21/52G06F21/74G06F21/82G06F2221/2101G06F2221/2105G06F2221/2141G06F2221/2143G06F2221/2149G06F2221/2153
    • A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
    • 在包括处理器核心,指令和数据高速缓冲存储器,写入缓冲器和写入缓冲器的处理器系统中,数字系统被提供有以非侵入式方式构建的安全模式(3级的特权级别) 内存管理单元。 因此,在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。 特别是操作系统不受信任,所有本地应用程序都不被信任。 提供了一种安全执行模式,当启用存储器管理单元(MMU)时允许虚拟寻址。 安全执行模式允许指令和数据高速缓存启用。 提供了一种安全执行模式,允许所有系统中断被隐藏。 通过唯一的入口点输入安全模式。 安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。 监视一个特定的条目条目,这些条目占用缓存,写入缓冲区和MMU被启用。 激活序列代码的结构用于缓存,写入缓冲区和MMU被使能。 退出序列代码的结构用于缓存,写入缓冲区和MMU被启用。 提供了一种具体的方法来管理通用中断下安全模式的安全退出,并允许从中断通过入口点和激活顺序返回,并适当恢复安全执行。 提供了以安全模式管理MMU的特定方式,并在安全和非安全环境之间提供数据交换。
    • 9. 发明授权
    • Secure mode for processors supporting MMU
    • 支持MMU的处理器的安全模式
    • US07120771B2
    • 2006-10-10
    • US10256596
    • 2002-09-27
    • Franck DahanChristian RousselAlain ChateauPeter Cumming
    • Franck DahanChristian RousselAlain ChateauPeter Cumming
    • G06F12/00
    • G06F21/556G06F9/30047G06F9/3802G06F9/468G06F12/1491G06F21/51G06F21/52G06F21/74G06F21/82G06F2221/2101G06F2221/2105G06F2221/2141G06F2221/2143G06F2221/2149G06F2221/2153
    • A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
    • 在包括处理器核心,指令和数据高速缓冲存储器,写入缓冲器和写入缓冲器的处理器系统中,数字系统被提供有以非侵入式方式构建的安全模式(3级的特权级别) 内存管理单元。 因此,在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。 特别是操作系统不受信任,所有本地应用程序都不被信任。 提供了一种安全执行模式,当启用存储器管理单元(MMU)时允许虚拟寻址。 安全执行模式允许指令和数据高速缓存启用。 提供了一种安全执行模式,允许所有系统中断被隐藏。 通过唯一的入口点输入安全模式。 安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。 监视一个特定的条目条目,这些条目占用缓存,写入缓冲区和MMU被启用。 激活序列代码的结构用于缓存,写入缓冲区和MMU被使能。 退出序列代码的结构用于缓存,写入缓冲区和MMU被启用。 提供了一种具体的方法来管理通用中断下安全模式的安全退出,并允许从中断通过入口点和激活顺序返回,并适当恢复安全执行。 提供了以安全模式管理MMU的特定方式,并在安全和非安全环境之间提供数据交换。