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1. 发明申请

US20190042689A1 ALIGNMENT KEY DESIGN RULE CHECK FOR CORRECT PLACEMENT OF ABUTTING CELLS IN AN INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20190042689A1
公开(公告)日：2019-02-07
申请号：US15670158
申请日：2017-08-07
申请人： GLOBALFOUNDRIES INC.
发明人： Nigel Chan , Germain Bossu
IPC分类号： G06F17/50
摘要： Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.

2. 发明申请

US20190019876A1 HIGH VOLTAGE TRANSISTOR USING BURIED INSULATING LAYER AS GATE DIELECTRIC 审中-公开
公开(公告)号：US20190019876A1
公开(公告)日：2019-01-17
申请号：US15647403
申请日：2017-07-12
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nigel Chan
IPC分类号： H01L29/51 , H01L29/66 , H01L29/165
摘要： A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

3. 发明授权

US09847347B1 Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof 有权
公开(公告)号：US09847347B1
公开(公告)日：2017-12-19
申请号：US15344856
申请日：2016-11-07
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nilesh Kenkare , Nigel Chan
IPC分类号： H01L27/12 , H01L29/51 , H01L29/45 , H01L29/417 , H01L29/66 , H01L21/84 , H01L21/311
CPC分类号： H01L27/1203 , H01L21/31144 , H01L21/84 , H01L29/41783 , H01L29/45 , H01L29/51 , H01L29/66545
摘要： A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.

4. 发明授权

US10593674B1 Deep fence isolation for logic cells 有权
公开(公告)号：US10593674B1
公开(公告)日：2020-03-17
申请号：US16129221
申请日：2018-09-12
申请人： GLOBALFOUNDRIES Inc.
发明人： Ming-Cheng Chang , Nigel Chan , Elliot John Smith
IPC分类号： H01L29/78 , H01L27/092 , H03K19/0948 , H01L21/762 , H01L29/423 , H01L21/8238 , H01L29/06 , H01L27/088 , H01L27/02
摘要： Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

5. 发明授权

US10319827B2 High voltage transistor using buried insulating layer as gate dielectric 有权
公开(公告)号：US10319827B2
公开(公告)日：2019-06-11
申请号：US15647403
申请日：2017-07-12
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nigel Chan
IPC分类号： H01L29/51 , H01L29/165 , H01L29/66
摘要： A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

6. 发明授权

US09768084B1 Inline monitoring of transistor-to-transistor critical dimension 有权
公开(公告)号：US09768084B1
公开(公告)日：2017-09-19
申请号：US15075378
申请日：2016-03-21
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nigel Chan
IPC分类号： H01L21/306 , H01L21/66 , H01L29/423 , H01L21/8234 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L22/30 , H01L21/30604 , H01L21/823456 , H01L21/84 , H01L22/12 , H01L27/11 , H01L27/1203 , H01L29/4236
摘要： In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

7. 发明申请

US20170077314A1 WAFER WITH SOI STRUCTURE HAVING A BURIED INSULATING MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE 有权
标题翻译：具有绝缘绝缘多层结构和半导体器件结构的SOI结构的晶体
公开(公告)号：US20170077314A1
公开(公告)日：2017-03-16
申请号：US14853146
申请日：2015-09-14
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Sven Beyer , Nigel Chan , Jan Hoentschel
IPC分类号： H01L29/792 , H01L29/06 , H01L21/326 , H01L29/423 , H01L21/762 , H01L29/66 , H01L29/08
CPC分类号： H01L29/7923 , H01L21/326 , H01L21/76254 , H01L21/76264 , H01L21/76283 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/42364 , H01L29/665 , H01L29/66833
摘要： The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.
摘要翻译：本公开在第一方面提供一种半导体器件结构，其包括：SOI衬底，其包括半导体基底衬底，形成在半导体基底衬底上的掩埋绝缘结构和形成在掩埋绝缘结构上的半导体膜，其中所述埋入绝缘结构包括具有介于两个氧化物层之间的氮化物层的多层堆叠。半导体器件结构还包括形成在SOI衬底的有源区中和之上的半导体器件，以及在半导体器件下电连接到半导体基底衬底的反偏压接触。

8. 发明授权

US09590118B1 Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure 有权
标题翻译：具有SOI结构的晶片，具有埋入式绝缘多层结构和半导体器件结构
公开(公告)号：US09590118B1
公开(公告)日：2017-03-07
申请号：US14853146
申请日：2015-09-14
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Sven Beyer , Nigel Chan , Jan Hoentschel
IPC分类号： H01L29/76 , H01L29/792 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/423 , H01L21/762 , H01L21/326
CPC分类号： H01L29/7923 , H01L21/326 , H01L21/76254 , H01L21/76264 , H01L21/76283 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/42364 , H01L29/665 , H01L29/66833
摘要： The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.
摘要翻译：本公开在第一方面提供一种半导体器件结构，其包括：SOI衬底，其包括半导体基底衬底，形成在半导体基底衬底上的掩埋绝缘结构和形成在掩埋绝缘结构上的半导体膜，其中所述埋入绝缘结构包括具有介于两个氧化物层之间的氮化物层的多层堆叠。半导体器件结构还包括形成在SOI衬底的有源区中和之上的半导体器件，以及在半导体器件下电连接到半导体基底衬底的反偏压接触。

9. 发明申请

US20160343428A1 DEVICE COMPRISING A PLURALITY OF FDSOI STATIC RANDOM-ACCESS MEMORY BITCELLS AND METHOD OF OPERATION THEREOF 有权
标题翻译：包含FDSOI静态随机存取存储器单元的多项设备及其操作方法
公开(公告)号：US20160343428A1
公开(公告)日：2016-11-24
申请号：US14718574
申请日：2015-05-21
申请人： GLOBALFOUNDRIES Inc.
发明人： Nigel Chan , Germain Bossu , Michael Otto
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , G11C11/418 , H01L27/1108
摘要： A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.
摘要翻译：一种包括以行和列排列的多个静态随机存取存储器（SRAM）位单元的器件，其中SRAM位单元包括完全耗尽的绝缘体上的硅场效应晶体管（FDSOI-FET）。 FDSOI-FET包括P沟道上拉晶体管，其中每个P沟道上拉晶体管包括一个后栅极。该设备还包括多个位线，其中每个位线电连接到一列的SRAM位单元和多个字线，其中每个字线电连接到其中一行的SRAM位单元。该装置还包括位线控制电路，其被配置为选择至少一个用于写入的列，其中在写入操作期间，将第一控制信号施加到至少一个列的P沟道上拉晶体管的背栅极选择用于写入的第二控制信号和未被选择用于写入的列的P沟道上拉晶体管的后栅极。

10. 发明申请

US20190319048A1 HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS 审中-公开
公开(公告)号：US20190319048A1
公开(公告)日：2019-10-17
申请号：US16446906
申请日：2019-06-20
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nigel Chan , Nilesh Kenkare
IPC分类号： H01L27/12 , H01L21/8234 , H01L21/84 , H01L21/266
摘要： One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

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