专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10504906B2 FinFET SRAM layout and method of making the same 有权
公开(公告)号：US10504906B2
公开(公告)日：2019-12-10
申请号：US15830671
申请日：2017-12-04
申请人： GLOBALFOUNDRIES Inc.
发明人： Ming-Cheng Chang , Nigel Chan , Ralf Van Bentum
IPC分类号： H01L27/11 , H01L21/8238 , H01L27/02 , H01L29/423 , H01L27/092
CPC分类号： H01L27/1104 , H01L21/823821 , H01L21/823828 , H01L27/0207 , H01L27/0924 , H01L29/42356
摘要： A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate over each of the fins, wherein all of the fins are diagonally skewed in a single direction relative to the gates, and all of the gates extend in a single direction relative to the respective fins.

2. 发明申请

US20190042689A1 ALIGNMENT KEY DESIGN RULE CHECK FOR CORRECT PLACEMENT OF ABUTTING CELLS IN AN INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20190042689A1
公开(公告)日：2019-02-07
申请号：US15670158
申请日：2017-08-07
申请人： GLOBALFOUNDRIES INC.
发明人： Nigel Chan , Germain Bossu
IPC分类号： G06F17/50
摘要： Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.

3. 发明申请

US20190019876A1 HIGH VOLTAGE TRANSISTOR USING BURIED INSULATING LAYER AS GATE DIELECTRIC 审中-公开
公开(公告)号：US20190019876A1
公开(公告)日：2019-01-17
申请号：US15647403
申请日：2017-07-12
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nigel Chan
IPC分类号： H01L29/51 , H01L29/66 , H01L29/165
摘要： A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

4. 发明授权

US09847347B1 Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof 有权
公开(公告)号：US09847347B1
公开(公告)日：2017-12-19
申请号：US15344856
申请日：2016-11-07
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nilesh Kenkare , Nigel Chan
IPC分类号： H01L27/12 , H01L29/51 , H01L29/45 , H01L29/417 , H01L29/66 , H01L21/84 , H01L21/311
CPC分类号： H01L27/1203 , H01L21/31144 , H01L21/84 , H01L29/41783 , H01L29/45 , H01L29/51 , H01L29/66545
摘要： A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.

5. 发明申请

US20190319048A1 HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS 审中-公开
公开(公告)号：US20190319048A1
公开(公告)日：2019-10-17
申请号：US16446906
申请日：2019-06-20
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nigel Chan , Nilesh Kenkare
IPC分类号： H01L27/12 , H01L21/8234 , H01L21/84 , H01L21/266
摘要： One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

6. 发明授权

US10396084B1 Semiconductor devices including self-aligned active regions for planar transistor architecture 有权
公开(公告)号：US10396084B1
公开(公告)日：2019-08-27
申请号：US15944910
申请日：2018-04-04
申请人： GLOBALFOUNDRIES Inc.
发明人： Elliot John Smith , Nigel Chan , Nilesh Kenkare , Hongsik Yoon
IPC分类号： H01L21/027 , H01L27/11 , H01L21/033 , H01L21/308
摘要： Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.

7. 发明授权

US10311201B2 Alignment key design rule check for correct placement of abutting cells in an integrated circuit 有权
公开(公告)号：US10311201B2
公开(公告)日：2019-06-04
申请号：US15670158
申请日：2017-08-07
申请人： GLOBALFOUNDRIES INC.
发明人： Nigel Chan , Germain Bossu
IPC分类号： G06F17/50
摘要： Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.

8. 发明授权

US10177163B1 SOI-based floating gate memory cell 有权
公开(公告)号：US10177163B1
公开(公告)日：2019-01-08
申请号：US15895053
申请日：2018-02-13
申请人： GLOBALFOUNDRIES Inc.
发明人： Nigel Chan , Elliot John Smith
IPC分类号： H01L23/02 , H01L27/11521 , H01L29/06 , H01L29/10 , H01L27/11558 , H01L21/762 , H01L29/66 , H01L29/788 , H01L27/12 , H01L21/28 , H01L21/306 , H01L21/308 , H01L21/02 , H01L21/3105 , H01L21/265 , H01L21/266
摘要： One illustrative device disclosed a floating gate capacitor located in and above a first region of an SOI substrate located on a first side of an isolation trench and a transistor device located in and above a second region of the SOI substrate that is on the opposite side of the isolation trench. The device also includes a control gate formed in the bulk semiconductor layer in the first region and a gate structure that extends across the isolation trench and above the first and second regions. A first portion of the gate structure is positioned above the first region and the control gate and a second portion of the gate structure is positioned above the second region, wherein the first portion of the gate structure constitutes a floating gate for the floating gate capacitor and the second portion of the gate structure constitutes a transistor gate structure for the transistor device.

9. 发明授权

US09762245B1 Semiconductor structure with back-gate switching 有权
公开(公告)号：US09762245B1
公开(公告)日：2017-09-12
申请号：US15182068
申请日：2016-06-14
申请人： GLOBALFOUNDRIES INC.
发明人： Michael Otto , Nigel Chan
IPC分类号： H03K19/00 , H03K19/094 , H03K19/0948 , H03K19/20
CPC分类号： H03K19/09429 , H03K19/09487 , H03K19/20
摘要： The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

10. 发明授权

US08921898B1 Device including an array of memory cells and well contact areas, and method for the formation thereof 有权
标题翻译：包括存储单元阵列和阱接触区域的装置及其形成方法
公开(公告)号：US08921898B1
公开(公告)日：2014-12-30
申请号：US13920780
申请日：2013-06-18
申请人： GLOBALFOUNDRIES Inc.
发明人： Nigel Chan , Michael Otto
IPC分类号： H01L27/118 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.
摘要翻译：一种器件包括多个存储器单元的阵列，至少一个N阱接触区域和至少一个P阱接触区域。存储单元布置成多行和多列。每列包括N阱区和至少一个P阱区。 N阱和P阱区域在柱的第一端和柱的第二端之间延伸。每个N阱接触区域电接触N阱区域中的至少一个，其中至少一个柱的N阱区域仅在柱的第一和第二端中的一个处电接触。每个P阱接触区域电接触至少一个P阱区域，其中至少一个柱的P阱区域仅在柱的第一和第二端中的一个处电接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式