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1. 发明申请

US20170194504A1 INTEGRATED CIRCUITS WITH GAPS 有权
公开(公告)号：US20170194504A1
公开(公告)日：2017-07-06
申请号：US14985607
申请日：2015-12-31
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Raj Verma Purakh , Shaoqiang Zhang , Rui Tze Toh
IPC分类号： H01L29/786 , H01L21/764 , H01L21/762
CPC分类号： H01L29/78603 , H01L21/76251 , H01L21/764 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of producing such integrated circuits are provided. In one example, an integrated circuit has a working layer that includes a semiconductor substrate. A handle layer underlies the working layer, where a gap is defined in the handle layer such that an upper gap surface underlies the working layer. The gap has a gap area measured along a first plane at the gap upper surface. A switch directly overlies the gap, where the switch has a switch area measured along a second plane parallel with the first plane. The switch area is less than the gap area.

2. 发明授权

US09960115B1 Heat dissipation and series resistance reduction of PA and RF switch in SLT by backside thick metal 有权
公开(公告)号：US09960115B1
公开(公告)日：2018-05-01
申请号：US15640928
申请日：2017-07-03
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Rui Tze Toh , Shyam Parthasarathy , Shaoqiang Zhang , Kouassi Sebastien Kouassi , Bo Yu , Raj Verma Purakh
IPC分类号： H01L29/40 , H01L23/522 , H01L21/768 , H01L27/12 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/762 , H01L21/7684 , H01L21/76883 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L27/1203
摘要： Methods of forming a SOI PA and RF switch device having a thin BOX layer in the PA power cell region and a thick metal layer directly under the thin BOX layer and the resulting device are provided. Embodiments include providing a SOI structure having a substrate, BOX, device and metallization layers; bonding a handling layer to the metallization layer; removing the substrate; forming a passivation oxide layer over the BOX; forming first and second trenches through the passivation, BOX, and device layers down to the metallization layer; forming a third trench through the passivation layer and a portion of the BOX above a PA power cell region of the SOI structure, a thin portion of the BOX remaining; forming a first backside contact in the first trench; and forming a second backside contact in the second and third trenches and over a portion of the passivation oxide layer.

3. 发明申请

US20170330896A1 INTEGRATED CIRCUITS WITH DEEP AND ULTRA SHALLOW TRENCH ISOLATIONS AND METHODS FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170330896A1
公开(公告)日：2017-11-16
申请号：US15151564
申请日：2016-05-11
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Guan Huei See , Rui Tze Toh , Shaoqiang Zhang , Purakh Raj Verma
IPC分类号： H01L27/12 , H01L21/84 , H01L29/06 , H01L29/49
CPC分类号： H01L27/1203 , H01L21/28123 , H01L21/84 , H01L29/0649 , H01L29/402 , H01L29/4975 , H01L29/66901 , H01L29/8086
摘要： Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.

4. 发明授权

US10529738B2 Integrated circuits with selectively strained device regions and methods for fabricating same 有权
公开(公告)号：US10529738B2
公开(公告)日：2020-01-07
申请号：US15140863
申请日：2016-04-28
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Raj Verma Purakh , Shaoqiang Zhang , Rui Tze Toh
IPC分类号： H01L29/66 , H01L29/778 , H01L29/10 , H01L29/78 , H01L27/12 , H01L21/762 , H01L21/02 , H01L21/84 , H01L21/3105 , H01L21/32 , H01L21/311 , H01L21/77
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.

5. 发明授权

US10020394B2 Extended drain metal-oxide-semiconductor transistor 有权
公开(公告)号：US10020394B2
公开(公告)日：2018-07-10
申请号：US15883056
申请日：2018-01-29
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Rui Tze Toh , Guan Huei See , Shaoqiang Zhang , Purakh Raj Verma
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10
CPC分类号： H01L29/7824 , H01L29/1095 , H01L29/665 , H01L29/66681 , H01L29/66689 , H01L29/66742 , H01L29/66772 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645
摘要： Devices and methods for forming a device are disclosed. A substrate is provided. A first body well of a second polarity type is formed in the substrate. A second body well of the second polarity type is formed in the first body well. A bottom of the second body well and a bottom of the first body well are contiguous. Dopant concentrations of the first and second body wells include a graded profile. A transistor of a first polarity type is formed over the substrate. The transistor includes a source and a drain. The source is formed in the second body well.

6. 发明申请

US20160276210A1 INTEGRATED CIRCUITS USING SILICON ON INSULATOR SUBSTRATES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：绝缘子基板上使用硅的集成电路及其制造方法
公开(公告)号：US20160276210A1
公开(公告)日：2016-09-22
申请号：US14662427
申请日：2015-03-19
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Rui Tze Toh , Guan Huei See , Shaoqiang Zhang , Raj Verma Purakh
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L21/28
CPC分类号： H01L21/76283 , H01L21/76205 , H01L21/76229 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211
摘要： Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a deep isolation block in an SOI substrate, where the SOI substrate includes a substrate layer overlying a buried insulator that in turn overlies a carrier wafer. The deep isolation block extends through the substrate layer and contacts the buried insulator. A shallow isolation block is formed in the substrate layer, where the shallow isolation block overlies a portion of the substrate layer. An isolation mask is formed overlying at least a portion of the deep isolation block to form a masked isolation block and an exposed isolation block, where the exposed isolation block includes the shallow isolation block. The exposed isolation block is removed such that a trough is defined in the substrate layer where the shallow isolation block was removed, and a gate is formed within the trough.
摘要翻译：提供了集成电路及其制造方法。一种集成电路的制造方法包括在SOI衬底中形成深度隔离块，其中SOI衬底包括覆盖在承载晶片上的掩埋绝缘体的衬底层。深的隔离块延伸穿过衬底层并接触埋入的绝缘体。在衬底层中形成浅的隔离块，其中浅隔离块覆盖衬底层的一部分。形成隔离掩模，覆盖深隔离块的至少一部分以形成掩蔽的隔离块和暴露的隔离块，其中暴露的隔离块包括浅隔离块。去除暴露的隔离块，使得在衬底层中限定了槽，其中浅隔离块被去除，并且在槽内形成栅极。

7. 发明授权

US10062710B2 Integrated circuits with deep and ultra shallow trench isolations and methods for fabricating the same 有权
公开(公告)号：US10062710B2
公开(公告)日：2018-08-28
申请号：US15151564
申请日：2016-05-11
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Guan Huei See , Rui Tze Toh , Shaoqiang Zhang , Purakh Raj Verma
IPC分类号： H01L21/84 , H01L27/12 , H01L29/06 , H01L29/49
CPC分类号： H01L27/1203 , H01L21/28123 , H01L21/762 , H01L21/76229 , H01L21/76283 , H01L21/84 , H01L29/0649 , H01L29/402 , H01L29/4975 , H01L29/66901 , H01L29/8086
摘要： Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.

8. 发明授权

US09922868B2 Integrated circuits using silicon on insulator substrates and methods of manufacturing the same 有权
公开(公告)号：US09922868B2
公开(公告)日：2018-03-20
申请号：US14662427
申请日：2015-03-19
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Rui Tze Toh , Guan Huei See , Shaoqiang Zhang , Raj Verma Purakh
IPC分类号： H01L27/12 , H01L21/762 , H01L21/84
CPC分类号： H01L21/76283 , H01L21/76205 , H01L21/76229 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211
摘要： Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a deep isolation block in an SOI substrate, where the SOI substrate includes a substrate layer overlying a buried insulator that in turn overlies a carrier wafer. The deep isolation block extends through the substrate layer and contacts the buried insulator. A shallow isolation block is formed in the substrate layer, where the shallow isolation block overlies a portion of the substrate layer. An isolation mask is formed overlying at least a portion of the deep isolation block to form a masked isolation block and an exposed isolation block, where the exposed isolation block includes the shallow isolation block. The exposed isolation block is removed such that a trough is defined in the substrate layer where the shallow isolation block was removed, and a gate is formed within the trough.

9. 发明授权

US09899527B2 Integrated circuits with gaps 有权
公开(公告)号：US09899527B2
公开(公告)日：2018-02-20
申请号：US14985607
申请日：2015-12-31
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Raj Verma Purakh , Shaoqiang Zhang , Rui Tze Toh
IPC分类号： H01L29/78 , H01L29/786 , H01L21/762 , H01L21/764
CPC分类号： H01L29/78603 , H01L21/76251 , H01L21/764 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of producing such integrated circuits are provided. In one example, an integrated circuit has a working layer that includes a semiconductor substrate. A handle layer underlies the working layer, where a gap is defined in the handle layer such that an upper gap surface underlies the working layer. The gap has a gap area measured along a first plane at the gap upper surface. A switch directly overlies the gap, where the switch has a switch area measured along a second plane parallel with the first plane. The switch area is less than the gap area.

10. 发明授权

US09087906B2 Grounding of silicon-on-insulator structure 有权
标题翻译：绝缘体上硅结构的接地
公开(公告)号：US09087906B2
公开(公告)日：2015-07-21
申请号：US14505483
申请日：2014-10-02
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Purakh Raj Verma , Shaoqiang Zhang , Bo Yu , Guan Huei See , Rui Tze Toh , Tao Jiang
IPC分类号： H01L29/786 , H01L29/66 , H01L21/02
CPC分类号： H01L29/78657 , H01L21/02381 , H01L21/02422 , H01L21/743 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/66477
摘要： Devices and methods for forming a device are presented. The method includes providing a substrate having at least a first region and a second region prepared with isolation regions. The first region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor is to be formed. The substrate includes a top surface layer, a support substrate and an insulator layer in between them. A transistor is formed in the second region and a substrate contact structure is formed in the first region. The substrate contact structure passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support substrate. The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level.
摘要翻译：提出了用于形成装置的装置和方法。该方法包括提供具有至少第一区域的基底和用隔离区域制备的第二区域。第一区域被称为芯片保护区域，第二区域限定要形成至少一个晶体管的芯片区域。衬底包括顶表面层，支撑衬底和它们之间的绝缘体层。晶体管形成在第二区域中，并且在第一区域中形成衬底接触结构。衬底接触结构至少穿过顶表面层，绝缘体层和隔离区并与支撑衬底中的掺杂区接触。衬底接触结构连接到具有期望电位的至少一个导电线，以防止在系统级别对支撑衬底的充电。

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