专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09218875B2 Resistive non-volatile memory 有权
标题翻译：电阻式非易失性存储器
公开(公告)号：US09218875B2
公开(公告)日：2015-12-22
申请号：US13802841
申请日：2013-03-14
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Yang Hong , Yong Wee Francis Poh , Tze Ho Simon Chan
IPC分类号： G11C11/00 , G11C13/00 , G11C7/10 , G11C11/56 , H01L45/00 , H01L27/22 , H01L27/24 , G11C8/16 , G11C11/16
CPC分类号： G11C13/0002 , G11C7/1075 , G11C8/16 , G11C11/161 , G11C11/1675 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2211/5641 , G11C2213/78 , G11C2213/79 , H01L27/224 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/146
摘要： A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the secondary selector selects a bit within the multi-bit cell. A plurality of storage units can be commonly coupled to a primary selector, facilitating high density applications.
摘要翻译：多位NVM单元包括具有诸如相变电阻元件之类的电阻元件的存储单元。 NVM单元可以配置为单端口或双端口多位单元。 NVM单元包括主单元选择器和次单元选择器。主选择器选择多位单元，而次选择器选择多位单元内的位。多个存储单元可以通常耦合到主选择器，便于高密度应用。

2. 发明授权

US09165610B1 Non-volatile memory cell arrays and methods of fabricating semiconductor devices 有权
标题翻译：非易失性存储单元阵列和制造半导体器件的方法
公开(公告)号：US09165610B1
公开(公告)日：2015-10-20
申请号：US14318766
申请日：2014-06-30
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Francis Poh , Shifeng Zhao , Yang Hong , Tze Ho Simon Chan
IPC分类号： G11C11/02 , G11C13/00 , G11C5/06 , G11C11/40 , G11C8/00 , G11C5/02 , G11C8/14 , H01L27/24 , G11C7/18
CPC分类号： G11C13/003 , G11C5/025 , G11C5/063 , G11C7/18 , G11C8/14 , G11C11/16 , G11C11/1657 , G11C11/1659 , G11C13/0002 , G11C13/0028 , G11C2213/74 , G11C2213/79 , G11C2213/82 , H01L27/2436
摘要： Disclosed herein are memory cell arrays, semiconductor devices, and methods for fabricating semiconductor devices. In one embodiment, a memory cell array includes first, second, third, and fourth memory cells each having a first transistor and a second transistor. First and second word-lines are coupled with the gates of the first transistors of the first and second memory cells. The second and a third word-line are coupled with the gates of the second transistors of the third and fourth memory cells.
摘要翻译：这里公开的是存储单元阵列，半导体器件和用于制造半导体器件的方法。在一个实施例中，存储单元阵列包括每个具有第一晶体管和第二晶体管的第一，第二，第三和第四存储单元。第一和第二字线与第一和第二存储器单元的第一晶体管的栅极耦合。第二和第三字线与第三和第四存储器单元的第二晶体管的栅极耦合。

3. 发明授权

US09196356B2 Stackable non-volatile memory 有权
标题翻译：可堆叠的非易失性存储器
公开(公告)号：US09196356B2
公开(公告)日：2015-11-24
申请号：US13802899
申请日：2013-03-14
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Yang Hong , Yong Wee Francis Poh , Tze Ho Simon Chan
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56 , H01L45/00 , H01L27/22 , H01L27/24 , G11C8/16 , G11C11/16
CPC分类号： G11C13/0004 , G11C8/16 , G11C11/161 , G11C11/1675 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C2213/71 , G11C2213/78 , G11C2213/79 , H01L27/228 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications.
摘要翻译：多位NVM单元包括具有诸如相变电阻元件之类的电阻元件的存储单元。 NVM单元可以配置为单端口或双端口多位单元。 NVM单元包括单元选择器。单元选择器选择多位单元。当适当的信号被施加到NVM单元时，单元选择器选择存储单元的适当的电阻元件。多个存储单元可以通常耦合到单元选择器，便于高密度应用。

4. 发明授权

US09082964B2 Nonvolative memory with filament 有权
标题翻译：非线性记忆与细丝
公开(公告)号：US09082964B2
公开(公告)日：2015-07-14
申请号：US14141478
申请日：2013-12-27
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Yang Hong , Yong Wee Francis Poh , Tze Ho Simon Chan
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1226 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1675 , H01L45/1691
摘要： An embodiment, relates to a phase changeable memory cell. The phase changeable memory cell is formed with an ultra small contact area formed by filament conductive path. This contact area between a heating electrode and phase changeable material layer is determined by the forming of filament path, which is conductive and much smaller in cross-sectional area than the minimum area that can be achieved by lithography. This leads to high heating efficiency and ultra-low programming current. As the disclosed structure has no requirement on endurance for the formed filament and use phase changeable material rather than filament-forming material to provide high on/off resistance ratio, drawbacks of filament-forming material on low endurance and low sensing margin are avoided in the proposed cell structure. Therefore, by using ReRAM-related filament-forming materials to get sub-litho-dimension conductive path as heating electrode and using high on/off ratio phase changeable material as the storage media, it is possible to reduce the power consumption of phase changeable memory dramatically without the drawbacks of filament-forming materials that are shown in ReRAM.
摘要翻译：实施例涉及可相变存储单元。相变存储单元形成有由细丝导电路径形成的超小接触面积。加热电极和相变材料层之间的该接触区域是通过形成导电的细丝线路的形成而确定的，并且比通过光刻可以获得的最小面积小得多的横截面面积。这导致高的加热效率和超低的编程电流。由于所公开的结构对成形的长丝的耐久性没有要求，并且使用相变材料而不是长丝形成材料来提供高的开/关电阻比，所以在低耐久性和低感测裕度的长丝形成材料的缺点在提出细胞结构。因此，通过使用与ReRAM相关的成丝材料来获得作为加热电极的亚光刻尺寸导电路径并使用高开/关比相变材料作为存储介质，可以降低相变存储器的功耗显着地没有ReRAM所示的成丝材料的缺点。

5. 发明授权

US09349772B2 Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM 有权
标题翻译：用自旋转矩传递磁性随机存取存储器（STT-MRAM）制造集成电路的方法包括沿着STT-MRAM的磁性隧道结的侧壁形成的钝化层
公开(公告)号：US09349772B2
公开(公告)日：2016-05-24
申请号：US14261543
申请日：2014-04-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Yang Hong , Yi Jiang , Francis Poh , Tze Ho Simon Chan , Juan Boon Tan
IPC分类号： H01L27/10 , H01L27/22 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12 , G11C11/16
CPC分类号： H01L27/222 , G11C11/16 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
摘要： A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.
摘要翻译：一种制造集成电路的方法包括在钝化层上方和钝化层的沟槽内沉积底部电极层，MTJ层和顶部电极层，并且去除MTJ层和顶部电极层的部分以形成 MTJ /顶部电极堆叠在底部电极层上方，并且至少部分地在沟槽的部分内被所述去除重新打开。该方法还包括在MTJ /顶部电极堆叠上形成另外的钝化层，形成另外的钝化层的另外的ILD层，以及在ILD层上和MTJ /顶部电极堆叠上重整顶部电极层。此外，该方法包括去除底部电极层，另外的钝化层，另外的ILD层和重新形成的顶部电极层的部分，以形成底部电极/ MTJ /顶部电极堆叠。

6. 发明授权

US09076962B2 Nonvolative memory 有权
标题翻译：非积极记忆
公开(公告)号：US09076962B2
公开(公告)日：2015-07-07
申请号：US14162721
申请日：2014-01-23
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Yang Hong , Yong Wee Francis Poh , Tze Ho Simon Chan
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1226 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/126 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1691
摘要： A phase changeable memory cell is disclosed. In an embodiment of the invention, a phase changeable memory cell is formed with an ultra-small contact area to reduce the programming current. This contact area between heater electrode and phase changeable material is limited by the thickness of thin films rather than lithographic critical dimension in one dimension. As a result, the contact area is much less than the square of lithographic critical dimension for almost every technology node, which is helps in reducing current. To further reduce the current and improve the heating efficiency, heater electrode is horizontally put with its length being tunable so as to minimize the heat loss flowing through the heater to the terminal that connects to the front end switch device. In addition, above and below the heater layer, low-thermal-conductivity material (LTCM) is used to minimize heat dissipation. This results in reduced power consumption of the phase changeable memory cell with improved reliability.
摘要翻译：公开了一种相变存储器单元。在本发明的一个实施例中，形成具有超小接触面积的相变存储单元以减少编程电流。加热器电极和相变材料之间的接触面积受到薄膜厚度的限制，而不是在一个维度上的光刻临界尺寸。因此，对于几乎每个技术节点，接触面积远小于光刻关键尺寸的平方，这有助于减少电流。为了进一步降低电流并提高加热效率，加热器电极被水平放置，其长度是可调的，以便使流过加热器的热损失最小化到连接到前端开关装置的端子。此外，在加热器层的上方和下方，使用低热导率材料（LTCM）来最小化散热。这导致相位可变的存储单元的功率消耗降低了可靠性。

7. 发明授权

US09583167B2 Low power memory cell with high sensing margin 有权
标题翻译：具有高感应余量的低功率存储单元
公开(公告)号：US09583167B2
公开(公告)日：2017-02-28
申请号：US14698882
申请日：2015-04-29
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Tze Ho Simon Chan , Yang Hong , Yong Wee Francis Poh
IPC分类号： G11C11/00 , G11C11/16 , H01L43/02 , H01L43/08 , H01L43/12 , H01L27/22
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12
摘要： Memory cell, method for operating the memory cell and method of forming the memory cell are disclosed. The memory cell includes a first selector having a first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, and a second selector having at least a second select transistor with a second gate coupled to a second wordline and first and second S/D regions. The memory cell includes a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D region of the first select transistor, and a second MTJ element coupled between a second bit line and the first S/D region of the second select transistor.
摘要翻译：公开了存储单元，用于操作存储单元的方法和形成存储单元的方法。存储单元包括具有第一选择晶体管的第一选择器，第一选择晶体管具有耦合到第一字线的第一栅极和第一和第二源极/漏极（S / D）区域，以及具有至少第二选择晶体管的第二选择器，具有第二栅极耦合到第二字线和第一和第二S / D区域。存储单元包括耦合在第一位线和第一选择晶体管的第一S / D区之间的第一磁隧道结（MTJ）元件，以及耦合在第二位线和第一S / D区之间的第二MTJ元件的第二选择晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式