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1. 发明授权

US07684968B1 Generation of a high-level simulation model of an electronic system by combining an HDL control function translated to a high-level language and a separate high-level data path function 有权
标题翻译：通过组合转换为高级语言的HDL控制功能和单独的高级数据路径功能来生成电子系统的高级仿真模型
公开(公告)号：US07684968B1
公开(公告)日：2010-03-23
申请号：US11010027
申请日：2004-12-09
申请人： Gabor Szedo , Singh Vinay Jitendra , L. James Hwang
发明人： Gabor Szedo , Singh Vinay Jitendra , L. James Hwang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Generating a high-level, bit-accurate and cycle-accurate simulation model. The various embodiments generate the simulation model from a functional description of a module and an HDL description of the module. The functional description may be un-timed and specified in a high-level language. The HDL description is realizable in hardware. The simulation model is created by obtaining the control specification from the HDL description and combining the control specification with the data path description from functional description.
摘要翻译：生成高级，位精度和循环精确的模拟模型。各种实施例从模块的功能描述和模块的HDL描述生成模拟模型。功能描述可以是高级语言的不及时和指定的。 HDL描述可以在硬件中实现。通过从HDL描述获得控制规范并将控制规范与功能描述中的数据路径描述相结合，创建仿真模型。

2. 发明授权

US07194705B1 Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions 有权
标题翻译：在使用硬件描述语言电路描述的高级建模系统中对集成电路进行仿真
公开(公告)号：US07194705B1
公开(公告)日：2007-03-20
申请号：US10388692
申请日：2003-03-14
申请人： Kumar Deepak , L. James Hwang , Singh Vinay Jitendra , Haibing Ma , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer , Jimmy Zhenming Wang
发明人： Kumar Deepak , L. James Hwang , Singh Vinay Jitendra , Haibing Ma , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer , Jimmy Zhenming Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.
摘要翻译：描述了使用电路的一个或多个电路描述语言表示来模拟建模系统内的集成电路的方法，装置和计算机可读介质。例如，电路的一个或多个电路描述语言表示的电路描述语言表示被转换成程序语言电路描述。执行第一模拟处理并从其获得输入数据。以输入数据作为参数输入来执行第二模拟处理以产生输出数据，第二模拟处理从程序语言电路描述导出。通过第二次模拟处理产生的输出数据被提供给第一个仿真过程。

3. 发明授权

US08042079B1 Synchronization for a modeling system 有权
标题翻译：建模系统的同步
公开(公告)号：US08042079B1
公开(公告)日：2011-10-18
申请号：US12468764
申请日：2009-05-19
申请人： Arvind Sundararajan , Haibing Ma , Andrew Dow , Singh Vinay Jitendra
发明人： Arvind Sundararajan , Haibing Ma , Andrew Dow , Singh Vinay Jitendra
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.
摘要翻译：描述了集成电路设备（“IC”）的高级建模系统（“HLMS”）的设计同步。在用于生成网表的方法中，将用户设计的第一电路块的描述输入到用计算机辅助建模系统编程的编程计算机系统。该描述包括第一电路块的输出端口信息和同步信号信息。计算机辅助建模系统响应于输出端口信息和同步信号信息，电路核心包括端口元数据，为第一电路块选择电路核心。计算机辅助建模系统响应于端口元数据选择至少一个宏来生成网表。该宏是用于将第一电路块与用户设计的第二电路块的速率同步耦合。计算机辅助建模系统输出包含宏的网表。

4. 发明授权

US07085976B1 Method and apparatus for hardware co-simulation clocking 有权
标题翻译：硬件协同仿真时钟的方法和装置
公开(公告)号：US07085976B1
公开(公告)日：2006-08-01
申请号：US10370023
申请日：2003-02-18
申请人： Nabeel Shirazi , Singh Vinay Jitendra
发明人： Nabeel Shirazi , Singh Vinay Jitendra
IPC分类号： G01R31/28
CPC分类号： G01R31/318516 , G01R31/318357 , G06F11/263 , G06F17/5022
摘要： Method and apparatus for hardware co-simulation clocking is described. More particularly, single-step clocking is used to load one or more test vectors and to output test results from such test vectors after processing. The test vectors are processed with the hardware using a free-running clock, for example to speed up test time and to generate information related to operational speed. A simulation of the hardware is used, where single-step clocking out the test results facilitates verification of the hardware test results with simulation test results.
摘要翻译：描述了用于硬件协同仿真时钟的方法和装置。更具体地，单步时钟用于加载一个或多个测试向量并且在处理之后从这些测试向量输出测试结果。使用自由运行时钟的硬件来处理测试向量，例如加快测试时间并产生与操作速度相关的信息。使用硬件的模拟，其中单步计时测试结果有助于通过仿真测试结果验证硬件测试结果。

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