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1. 发明授权

US08811060B2 Non-volatile memory crosspoint repair 有权
标题翻译：非易失性存储器交叉点修复
公开(公告)号：US08811060B2
公开(公告)日：2014-08-19
申请号：US13485748
申请日：2012-05-31
申请人： Geoffrey W. Burr , Rohit S. Shenoy , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Rohit S. Shenoy , Kailash Gopalakrishnan
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译：一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。还介绍了其他系统和方法。

2. 发明申请

US20130322153A1 NON-VOLATILE MEMORY CROSSPOINT REPAIR 有权
标题翻译：非挥发性记忆修复修复
公开(公告)号：US20130322153A1
公开(公告)日：2013-12-05
申请号：US13485748
申请日：2012-05-31
申请人： Geoffrey W. Burr , Kailash Gopalakrishnan , Rohit S. Shenoy
发明人： Geoffrey W. Burr , Kailash Gopalakrishnan , Rohit S. Shenoy
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译：一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。还介绍了其他系统和方法。

3. 发明申请

US20080280401A1 INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES 有权
标题翻译：存储器阵列中增加有效半导体晶体管
公开(公告)号：US20080280401A1
公开(公告)日：2008-11-13
申请号：US12180586
申请日：2008-07-28
申请人： Geoffrey W. Burr , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Kailash Gopalakrishnan
IPC分类号： H01L21/84
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2216/10
摘要： A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
摘要翻译：一种用于形成存储器结构的方法，包括：形成布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元还包括能够被编程为多个电阻状态的电阻性存储器件每个电阻存储器件在其第一端处耦合到位线之一; 在其第二端配置与每个所述电阻式存储器件串联的整流元件; 配置与每个单独存储器单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及形成公共连接，其被配置为沿着字线方向将两个或更多个组的相邻整流装置短路在一起。

4. 发明申请

US20080225567A1 METHOD AND STRUCTURE FOR INCREASING EFFECTIVE TRANSISTOR WIDTH IN MEMORY ARRAYS WITH DUAL BITLINES 失效
标题翻译：用双比特增加存储器阵列中有效晶体管宽度的方法和结构
公开(公告)号：US20080225567A1
公开(公告)日：2008-09-18
申请号：US11686415
申请日：2007-03-15
申请人： Geoffrey W. Burr , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Kailash Gopalakrishnan
IPC分类号： G11C17/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2216/10
摘要： A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
摘要翻译：存储器结构包括：布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元进一步包括能够被编程为多个电阻状态的电阻性存储器件，每个电阻状态在其第一端耦合到位线中的一个的存储器件; 整流元件，其每个电阻存储器件在其第二端处串联; 与每个单独的存储单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及公共连接，其被配置为沿着字线方向以两个或更多个组的形式将相邻整流装置短路。

5. 发明授权

US07447062B2 Method and structure for increasing effective transistor width in memory arrays with dual bitlines 失效
标题翻译：在双位线存储器阵列中提高有效晶体管宽度的方法和结构
公开(公告)号：US07447062B2
公开(公告)日：2008-11-04
申请号：US11686415
申请日：2007-03-15
申请人： Geoffrey W. Burr , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Kailash Gopalakrishnan
IPC分类号： G11C11/00 , G11C5/06
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2216/10
摘要： A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
摘要翻译：存储器结构包括：布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元进一步包括能够被编程为多个电阻状态的电阻性存储器件，每个电阻状态在其第一端耦合到位线中的一个的存储器件; 整流元件，其每个电阻存储器件在其第二端处串联; 与每个单独的存储单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及公共连接，其被配置为沿着字线方向以两个或更多个组的形式将相邻整流装置短路。

6. 发明授权

US07920406B2 Increasing effective transistor width in memory arrays with dual bitlines 有权
标题翻译：在双位线存储器阵列中增加有效的晶体管宽度
公开(公告)号：US07920406B2
公开(公告)日：2011-04-05
申请号：US12180586
申请日：2008-07-28
申请人： Geoffrey W. Burr , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Kailash Gopalakrishnan
IPC分类号： G11C11/00 , G11C5/06
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2216/10
摘要： A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
摘要翻译：一种用于形成存储器结构的方法，包括：形成布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元还包括能够被编程为多个电阻状态的电阻性存储器件每个电阻存储器件在其第一端处耦合到位线之一; 在其第二端配置与每个所述电阻式存储器件串联的整流元件; 配置与每个单独存储器单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及形成公共连接，其被配置为沿着字线方向将两个或更多个组的相邻整流装置短路在一起。

7. 发明申请

US20080225578A1 STRUCTURE FOR INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES 审中-公开
标题翻译：增加有效半导体存储器阵列中有效半导体结构的结构
公开(公告)号：US20080225578A1
公开(公告)日：2008-09-18
申请号：US12055907
申请日：2008-03-26
申请人： Geoffrey W. Burr , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Kailash Gopalakrishnan
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2216/10
摘要： A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
摘要翻译：存储器结构包括：布置在位线和字线的网络中的各个存储单元的阵列，每个独立存储单元进一步包括能够被编程为多个电阻状态的电阻性存储器件，每个电阻状态在其第一端耦合到位线中的一个的存储器件; 整流元件，其每个电阻存储器件在其第二端处串联; 与每个单独的存储单元相关联的存取晶体管，所述存取晶体管由施加到对应的一条字线的信号激活，每个存取晶体管与相应的整流元件串联; 以及公共连接，其被配置为沿着字线方向以两个或更多个组的形式将相邻整流装置短路。

8. 发明授权

US07968861B2 Phase change memory element 失效
标题翻译：相变存储元件
公开(公告)号：US07968861B2
公开(公告)日：2011-06-28
申请号：US12130075
申请日：2008-05-30
申请人： Geoffrey W. Burr , Yi-Chou Chen , Hsiang-Lan Lung
发明人： Geoffrey W. Burr , Yi-Chou Chen , Hsiang-Lan Lung
IPC分类号： H01L45/00
CPC分类号： H01L45/122 , G11C13/0004 , G11C2213/55 , H01L45/06 , H01L45/1675
摘要： Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.
摘要翻译：具有通过重叠薄膜形成的具有小的相变开关体积的薄膜相变存储器。示例性实施例包括相变存储元件，包括具有电阻的第一相变层，具有电阻的第二相变层，设置在第一和第二相变层之间的绝缘层; 以及具有电阻的第三相变层，并且耦合到所述第一和第二相变层中的每一个，桥接所述绝缘层并电耦合所述第一和第二相变层，其中所述第三相变层的电阻大于第一相变层和第二相变层的电阻。

9. 发明申请

US20080272356A1 FABRICATION OF PHASE CHANGE MEMORY ELEMENT WITH PHASE-CHANGE ELECTRODES USING CONFORMAL DEPOSITION 失效
公开(公告)号：US20080272356A1
公开(公告)日：2008-11-06
申请号：US12173406
申请日：2008-07-15
申请人： Geoffrey W. Burr
发明人： Geoffrey W. Burr
IPC分类号： H01L47/00
CPC分类号： G11C13/0004 , G11C2213/55 , H01L45/06 , H01L45/122 , H01L45/1666
摘要： A phase change memory element with phase change electrodes, and method of making the same. Exemplary embodiments include a phase change bridge, including a bottom contact layer, a first insulating layer disposed on the bottom contact layer, a first phase change region disposed on the bottom contact layer adjacent the first insulating layer, a second phase change region disposed on the bottom contact layer adjacent the first insulating layer, wherein the first insulating layer thermally and electrically isolates the first and second phase change regions, and a third phase change region disposed on each of the first and second phase change regions, each of the third phase change regions isolated from one another by a conductor layer disposed on the first insulating layer.

10. 发明申请

US20080179583A1 FABRICATION OF PHASE CHANGE MEMORY ELEMENT WITH PHASE-CHANGE ELECTRODES USING CONFORMAL DEPOSITION 有权
标题翻译：使用一致的沉积制备相变电极相变记忆元件
公开(公告)号：US20080179583A1
公开(公告)日：2008-07-31
申请号：US11668224
申请日：2007-01-29
申请人： Geoffrey W. Burr
发明人： Geoffrey W. Burr
IPC分类号： H01L45/00
CPC分类号： G11C13/0004 , G11C2213/55 , H01L45/06 , H01L45/122 , H01L45/1666
摘要： A phase change memory element with phase change electrodes, and method of making the same. Exemplary embodiments include a phase change bridge, including a bottom contact layer, a first insulating layer disposed on the bottom contact layer, a first phase change region disposed on the bottom contact layer adjacent the first insulating layer, a second phase change region disposed on the bottom contact layer adjacent the first insulating layer, wherein the first insulating layer thermally and electrically isolates the first and second phase change regions, and a third phase change region disposed on each of the first and second phase change regions, each of the third phase change regions isolated from one another by a conductor layer disposed on the first insulating layer.
摘要翻译：具有相变电极的相变存储元件及其制造方法。示例性实施例包括相变桥，包括底部接触层，设置在底部接触层上的第一绝缘层，设置在与第一绝缘层相邻的底部接触层上的第一相变区域，设置在第二绝缘层上的第二相变区域底部接触层，其中所述第一绝缘层热和电隔离所述第一和第二相变区域，以及设置在所述第一和第二相变区域中的每一个上的第三相变区域，所述第三相变区域中的每一个通过布置在第一绝缘层上的导体层彼此隔离的区域。

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