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    • 3. 发明申请
    • Mobile Commerce Authentication And Authorization Systems
    • 移动商务认证和授权系统
    • US20110131104A1
    • 2011-06-02
    • US12789722
    • 2010-05-28
    • Gregory Gordon RoseCraig B. LauerJoan T. Waltman
    • Gregory Gordon RoseCraig B. LauerJoan T. Waltman
    • G06Q20/00G06K19/00G06K19/06
    • G06Q20/32G06Q20/20G06Q20/204G06Q20/425
    • Mobile commerce authentication and authorization systems enable currently existing point-of-sale devices that are neither structurally nor systemically altered to conduct financial transactions with a customer using an access terminal across a wireless communications system. The point-of-sale devices receive an input from a payment instrument replacement, which identifies the transaction to the point-of-sale device as a transaction including an access terminal. Authentication of the user of the access terminal is achieved at least by application of position and/or location determinable features of the access terminal, the position and/or location of a point-of-sale device of a vendor or merchant where the customer seeks to purchase goods or services, and the payment sum entered on the point-of-sale device. A payment matching server may assist in processing the location data and the payment sum amount across communications network.
    • 移动商务认证和授权系统使得当前现有的销售点设备既不在结构上也不是系统地改变,以便通过无线通信系统使用接入终端与客户进行金融交易。 销售点设备从支付工具替换中接收输入,该替换将识别到作为包括接入终端的交易的销售点设备的交易。 至少通过应用接入终端的位置和/或位置确定特征,客户寻求的供应商或商家的销售点设备的位置和/或位置来实现接入终端的用户的认证 购买商品或服务,以及在销售点设备上输入的付款金额。 支付匹配服务器可以协助处理跨通信网络的位置数据和支付金额。
    • 9. 发明授权
    • Pulse density modulation circuit (parallel to serial) comparing in a
nonsequential bit order
    • 脉冲密度调制电路(并行串行)以非顺序比特顺序进行比较
    • US5337338A
    • 1994-08-09
    • US11618
    • 1993-02-01
    • Todd SuttonSherman GregoryJoan T. WaltmanKatherine W. White
    • Todd SuttonSherman GregoryJoan T. WaltmanKatherine W. White
    • H03M5/04H03M7/00H03K21/14
    • H03M5/04
    • A pulse density modulation circuit has a counter which produces a most significant bit through a least significant bit output based on a clock input. The circuit also has a comparator with two sets of most significant bit through least significant bit inputs that produces an output based on a comparison of the two sets of inputs. The first set of comparator most significant bit through least significant bit inputs receives respectively a most significant bit through a least significant bit of an input reference signal. The second set of comparator most significant bit through least significant bit inputs receives the counter most significant bit through least significant bit output in a non-sequential bit order. The non-sequential bit order can be a bit reversed order wherein the counter most significant bit through least significant bit output are respectively connected to the comparator least significant bit through most significant bit input. The circuit may further filter the comparator output to provide a resultant analog output signal.
    • 脉冲密度调制电路具有基于时钟输入通过最低有效位输出产生最高有效位的计数器。 该电路还具有比较器,其具有两组最高有效位通过最低有效位输入,其基于两组输入的比较产生输出。 第一组比较器最高有效位通过最低有效位输入通过输入参考信号的最低有效位分别接收最高有效位。 第二组比较器最高有效位通过最低有效位输入以非顺序位顺序通过最低有效位输出接收计数器最高有效位。 非顺序位顺序可以是位反转顺序,其中通过最低有效位输出的计数器最高有效位分别通过最高有效位输入连接到比较器最低有效位。 电路可以进一步对比较器输出进行滤波以提供合成的模拟输出信号。