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1. 发明授权

US07958071B2 Computational nodes and computational-node networks that include dynamical-nanodevice connections 有权
标题翻译：包括动态 - 纳联设备连接的计算节点和计算节点网络
公开(公告)号：US07958071B2
公开(公告)日：2011-06-07
申请号：US11788447
申请日：2007-04-19
申请人： Gregory S. Snider , Warren J. Robinett
发明人： Gregory S. Snider , Warren J. Robinett
IPC分类号： G06E1/00
CPC分类号： G06N3/063
摘要： Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.
摘要翻译：本发明的实施例采用动态纳米级器件，包括纳米线之间的忆阻连接，用于构建并行，分布式，动态计算网络和包括感知器网络和神经网络的系统。在本发明的许多实施例中，类似神经元的计算设备由硅基微尺度和/或亚微米级元件构成，并且通过包括纳米线和纳米线之间的忆阻连接的动态互连彼此互连。在许多大规模并行，分布式，动态计算系统（包括人类大脑）中，可能存在比神经元状计算节点更多的互连数。对这些连接使用动态纳米级器件可以产生巨大的设计，空间，能量和计算效率。

2. 发明申请

US20080258767A1 Computational nodes and computational-node networks that include dynamical-nanodevice connections 有权
标题翻译：包括动态 - 纳联设备连接的计算节点和计算节点网络
公开(公告)号：US20080258767A1
公开(公告)日：2008-10-23
申请号：US11788447
申请日：2007-04-19
申请人： Gregory S. Snider , Warren J. Robinett
发明人： Gregory S. Snider , Warren J. Robinett
IPC分类号： G06F7/38
CPC分类号： G06N3/063
摘要： Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.
摘要翻译：本发明的实施例采用动态纳米级器件，包括纳米线之间的忆阻连接，用于构建并行，分布式，动态计算网络和包括感知器网络和神经网络的系统。在本发明的许多实施例中，类似神经元的计算设备由硅基微尺度和/或亚微米级元件构成，并且通过包括纳米线和纳米线之间的忆阻连接的动态互连彼此互连。在许多大规模并行，分布式，动态计算系统（包括人类大脑）中，可能存在比神经元状计算节点更多的互连数。对这些连接使用动态纳米级器件可以产生巨大的设计，空间，能量和计算效率。

3. 发明授权

US08812418B2 Memristive adaptive resonance networks 有权
标题翻译：记忆自适应共振网络
公开(公告)号：US08812418B2
公开(公告)日：2014-08-19
申请号：US13256246
申请日：2009-06-22
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063
摘要： A method for implementing an artificial neural network includes connecting a plurality of receiving neurons to a plurality of transmitting neurons through memristive synapses. Each memristive synapse has a weight which is initialized into a conductive state. A binary input vector is presented through the memristive synapses to the plurality of receiving neurons and the state of one or more of the memristive synapses modified based on the binary input vector.
摘要翻译：一种用于实现人造神经网络的方法包括通过忆阻突触将多个接收神经元连接到多个发射神经元。每个忆阻突触的重量都被初始化为导电状态。通过对多个接收神经元的忆阻突触呈现二进制输入向量，并且基于二进制输入向量修改的一个或多个忆阻突触的状态。

4. 发明授权

US08166860B2 System for forming a miter joint 有权
标题翻译：用于形成斜接接头的系统
公开(公告)号：US08166860B2
公开(公告)日：2012-05-01
申请号：US12848427
申请日：2010-08-02
申请人： Louis Gibbons , Gregory S. Snider , Frederick R. Bean , Terry L. Turner , Steven McClaskey , Robert H. Gifford
发明人： Louis Gibbons , Gregory S. Snider , Frederick R. Bean , Terry L. Turner , Steven McClaskey , Robert H. Gifford
IPC分类号： B23D45/14 , B23D45/04 , B23D47/04
CPC分类号： B27B27/08 , B23D45/042 , B27B5/29 , B27B27/10 , B27G5/023 , Y10T83/762 , Y10T83/7705 , Y10T83/773 , Y10T83/865
摘要： The present invention is directed toward a system for forming miter joints including a miter saw and an angle gauge. The miter saw includes a platform with a kerf slot and a pair of arcuate slots. Each arcuate slot includes an associated rail located on the underside of the platform. A fence is coupled to each of the rails such that the fence may be pivoted with respect to the platform. The angle measurement tool is a one-handed tool including spring loaded paddles that measure the angle between intersecting surfaces. The angle measurement tool connects to the miter saw to permit the transfer of the measured angle to the fences.
摘要翻译：本发明涉及一种用于形成包括斜切锯和角度计的斜接头的系统。斜切锯包括具有切口槽和一对弓形槽的平台。每个弧形槽包括位于平台下侧的相关导轨。栅栏连接到每个轨道，使得围栏可以相对于平台枢转。角度测量工具是一个单手工具，包括弹簧加载桨叶，用于测量相交表面之间的角度。角度测量工具连接到斜切锯，以允许将测量的角度传递到围栏。

5. 发明申请

US20120016829A1 Memristive Adaptive Resonance Networks 有权
标题翻译：记忆自适应谐振网络
公开(公告)号：US20120016829A1
公开(公告)日：2012-01-19
申请号：US13256246
申请日：2009-06-22
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063
摘要： A method for implementing an artificial neural network includes connecting a plurality of receiving neurons to a plurality of transmitting neurons through memristive synapses (705). Each memristive synapse has a weight which is initialized into a conductive state (715). A binary input vector is presented through the memristive synapses to the plurality of receiving neurons (735) and the state of one or more of the memristive synapses modified based on the binary input vector (760).
摘要翻译：实现人造神经网络的方法包括通过忆阻突触将多个接收神经元连接到多个发射神经元（705）。每个忆阻突触具有初始化为导电状态的重量（715）。通过对多个接收神经元（735）的忆阻突触呈现二进制输入向量，并且基于二进制输入向量（760）修改的一个或多个忆阻突触的状态。

6. 发明授权

US07720377B2 Compute clusters employing photonic interconnections for transmitting optical signals between compute cluster nodes 有权
标题翻译：使用光子互连计算集群，用于在计算集群节点之间传输光信号
公开(公告)号：US07720377B2
公开(公告)日：2010-05-18
申请号：US11337328
申请日：2006-01-23
申请人： Gregory S. Snider , Raymond Beausoleil
发明人： Gregory S. Snider , Raymond Beausoleil
IPC分类号： H04J14/00
CPC分类号： H04Q11/0001 , B82Y10/00 , B82Y20/00 , G02B6/1225 , G02B6/43 , G06N99/002 , H04B10/801 , H04L49/101 , H04L49/254 , H04L49/3045 , H04L49/357
摘要： Various embodiments of the present invention are directed to photonic-interconnection-based compute clusters that provide high-speed, high-bandwidth interconnections between compute cluster nodes. In one embodiment of the present invention, the compute cluster includes a photonic interconnection having one or more optical transmission paths for transmitting independent frequency channels within an optical signal to each node in a set of nodes. The compute cluster includes one or more photonic-interconnection-based writers, each writer associated with a particular node, and each writer encoding information generated by the node into one of the independent frequency channels. A switch fabric directs the information encoded in the independent frequency channels to one or more nodes in the compute cluster. The compute cluster also includes one or more photonic-interconnection-based readers, each reader associated with a particular node, and each reader extracting the information encoded in the independent frequency channels directed to the node for processing.
摘要翻译：本发明的各种实施例涉及在计算集群节点之间提供高速，高带宽互连的基于光子互连的计算集群。在本发明的一个实施例中，计算集群包括具有一个或多个光传输路径的光子互连，用于将光信号内的独立频率信道传送到一组节点中的每个节点。计算集群包括一个或多个基于光子互连的写入器，每个写入器与特定节点相关联，并且每个写入器将由节点生成的信息编码为独立频率信道之一。交换结构将在独立频率信道中编码的信息定向到计算集群中的一个或多个节点。计算集群还包括一个或多个基于光子互连的读取器，每个读取器与特定节点相关联，并且每个读取器提取在指向节点的独立频率信道中编码的信息进行处理。

7. 发明授权

US07652911B2 Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers 有权
标题翻译：使用微米/纳米级移位寄存器的纳米级移位寄存器和信号解复用
公开(公告)号：US07652911B2
公开(公告)日：2010-01-26
申请号：US12331642
申请日：2008-12-10
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0023 , G11C19/00 , G11C2213/17 , G11C2213/77 , G11C2213/81
摘要： Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.
摘要翻译：用于将数据值图案输入到纳米线交叉开关中的方法，用于将数据值图案输入到支持存储在计算机可读介质中的计算机指令的纳米线交叉开关中，以及用于将接收到的数据值分配到一组纳米线中的每一个提供了在逻辑电路中实现的支持控制逻辑。采用第一和第二纳米级移位寄存器，第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度的移动寄存器，。值的第一模式被存储在第一移位寄存器中，并且第二模式的值被存储在第二移位寄存器中，该电压信号低于用于交叉开关的接点的写电压。施加大于或等于WRITE阈值的电压信号用于交叉开关的交叉点，以将数据值的模式写入交叉开关。

8. 发明授权

US07444495B1 Processor and programmable logic computing arrangement 失效
标题翻译：处理器和可编程逻辑计算安排
公开(公告)号：US07444495B1
公开(公告)日：2008-10-28
申请号：US10232970
申请日：2002-08-30
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G06F9/455 , G06F15/163
CPC分类号： G06F9/30174 , G06F9/45504
摘要： A computing arrangement including a processor and programmable logic. In various embodiments, the arrangement includes an instruction processing circuit coupled to a programmable logic circuit, and a memory arrangement coupled to the instruction processing circuit and to the programmable logic circuit. The instruction processing circuit executes instructions of a native instruction set, and the programmable logic is configured to dynamically translate input instructions to translated instructions of the native instruction set. The translated instructions are stored in a translation cache in the memory arrangement, and the translation cache is managed by the programmable logic. The programmable logic then provides the translated instructions to the instruction processing circuit for execution.
摘要翻译：一种包括处理器和可编程逻辑的计算装置。在各种实施例中，该装置包括耦合到可编程逻辑电路的指令处理电路和耦合到指令处理电路和可编程逻辑电路的存储器装置。指令处理电路执行本地指令集的指令，并且可编程逻辑被配置为将输入指令动态地转换为本地指令集的转换指令。翻译的指令被存储在存储器装置中的转换高速缓存中，并且转换高速缓存由可编程逻辑管理。然后，可编程逻辑将转换的指令提供给指令处理电路以供执行。

9. 发明授权

US07436209B1 Nanoscale electronic latch 有权
标题翻译：纳米级电子锁
公开(公告)号：US07436209B1
公开(公告)日：2008-10-14
申请号：US11590491
申请日：2006-10-30
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H03K19/177
CPC分类号： H01L27/10 , B82Y10/00 , H01L29/0665 , H01L29/0673
摘要： In one embodiment of the present invention, a nanoscale latch is implemented by interconnecting an enable line, two control lines, and a pull-down line, when needed, to a signal line carrying encoded binary values to be latched and subsequently output. The enable line is interconnected with the signal line through a field-effect-transistor-like nanoscale junction. Both control lines are interconnected with the signal line through asymmetric-switch nanoscale junctions of like polarities. The pull-down line, when needed, is interconnected with the signal line through a resistive nanoscale junction. Inputting a sequence of signals to the enable and control lines allows a value input from the signal line to be stored and subsequently output to the signal line. In various additional embodiments, an array of nanoscale latches can be implemented by overlaying enable and control lines, and a pull-down line when needed, over a set of parallel nanowires.
摘要翻译：在本发明的一个实施例中，纳米尺度锁存器通过在需要时将使能线，两条控制线和下拉线互连到一个承载要锁存并随后输出的编码二进制值的信号线来实现。使能线通过场效应晶体管状纳米级结与信号线互连。两个控制线通过具有相似极性的非对称开关纳米级结与信号线互连。当需要时，下拉线通过电阻性纳米级结与信号线互连。将一系列信号输入到使能和控制线路允许从信号线输入的值被存储并随后输出到信号线。在各种附加实施例中，纳米尺度锁存器的阵列可以通过在一组平行纳米线上覆盖使能和控制线以及需要时的下拉线来实现。

10. 外观设计

USD573459S1 Reusable packaging for a light line generating device 有权
标题翻译：用于光线生成装置的可重复使用的包装
公开(公告)号：USD573459S1
公开(公告)日：2008-07-22
申请号：US29278255
申请日：2007-03-23
申请人： Gregory S. Snider , Marc Salois
设计人： Gregory S. Snider , Marc Salois

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