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1. 发明授权

US08370595B2 Aggregate data processing system having multiple overlapping synthetic computers 有权
标题翻译：具有多个重叠合成计算机的综合数据处理系统
公开(公告)号：US08370595B2
公开(公告)日：2013-02-05
申请号：US12643800
申请日：2009-12-21
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

2. 发明申请

US20120324189A1 AGGREGATE DATA PROCESSING SYSTEM HAVING MULTIPLE OVERLAPPING SYNTHETIC COMPUTERS 有权
标题翻译：具有多重叠加合成计算机的综合数据处理系统
公开(公告)号：US20120324189A1
公开(公告)日：2012-12-20
申请号：US13599856
申请日：2012-08-30
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/14
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

3. 发明申请

US20110153943A1 Aggregate Data Processing System Having Multiple Overlapping Synthetic Computers 有权
标题翻译：具有多重重合成计算机的综合数据处理系统
公开(公告)号：US20110153943A1
公开(公告)日：2011-06-23
申请号：US12643800
申请日：2009-12-21
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/14 , G06F12/08
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

4. 发明授权

US08656128B2 Aggregate data processing system having multiple overlapping synthetic computers 有权
标题翻译：具有多个重叠合成计算机的综合数据处理系统
公开(公告)号：US08656128B2
公开(公告)日：2014-02-18
申请号：US13599856
申请日：2012-08-30
申请人： Guy L Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

5. 发明申请

US20090198971A1 Heterogeneous Processing Elements 有权
标题翻译：异构处理元件
公开(公告)号：US20090198971A1
公开(公告)日：2009-08-06
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
IPC分类号： G06F9/30
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, power perspective, as the processors. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元素模型将特殊处理元素放在与处理器相同的竞争环境中，从编程角度，操作系统的角度，功率视角，作为处理器。操作系统可以使用安全引擎，例如，与处理器相同。

6. 发明授权

US08893126B2 Binding a process to a special purpose processing element having characteristics of a processor 有权
标题翻译：将过程绑定到具有处理器特征的专用处理元件
公开(公告)号：US08893126B2
公开(公告)日：2014-11-18
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
IPC分类号： G06F9/00 , G06F13/12
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, and power perspective. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元素模型将特殊处理元素与编程角度，操作系统角度和功能视角相结合，将处理器与处理器相同。操作系统可以使用安全引擎，例如，与处理器相同。

7. 发明授权

US06803922B2 Pixel formatter for two-dimensional graphics engine of set-top box system 失效
标题翻译：用于机顶盒系统的二维图形引擎的像素格式化器
公开(公告)号：US06803922B2
公开(公告)日：2004-10-12
申请号：US10077563
申请日：2002-02-14
申请人： Charles F. Marino
发明人： Charles F. Marino
IPC分类号： G01G502
CPC分类号： G06T1/00
摘要： A technique is provided for aligning and formatting multi-operand pixel data, for example, within a pixel formatter of a graphics engine for a set-top box system. The technique includes, in one embodiment, obtaining pixel data of a first alignment and a first format for conversion to a second alignment and a second format. The pixel data undergoes pre-alignment where the first alignment of the pixel data is changed to a bit zero alignment, after which the pixel data is reformatted from the first format to the second format. The reformatted pixel data is post-aligned to change from bit zero alignment to the second alignment. In one embodiment, the pixel data is source pixel data or pattern pixel data, while the second alignment and the second format are alignment and format of destination pixel data.
摘要翻译：提供了一种用于对准和格式化多操作数像素数据的技术，例如在用于机顶盒系统的图形引擎的像素格式化器内。在一个实施例中，该技术包括获得第一对准的像素数据和用于转换为第二对准和第二格式的第一格式。像素数据经历预对准，其中像素数据的第一对准被改变为位零对准，之后将像素数据从第一格式重新格式化为第二格式。重新格式化的像素数据被对准以从位零对准改变到第二对准。在一个实施例中，像素数据是源像素数据或图案像素数据，而第二对准和第二格式是目标像素数据的对准和格式。

8. 发明授权

US06061403A Computer program product for selectively reducing bandwidth of real-time video data 失效
标题翻译：用于选择性降低实时视频数据带宽的计算机程序产品
公开(公告)号：US06061403A
公开(公告)日：2000-05-09
申请号：US353558
申请日：1999-07-15
申请人： Charles F. Marino
发明人： Charles F. Marino
IPC分类号： H04B1/66 , H04N7/12 , H04N7/26 , H04N7/32
CPC分类号： H04N19/423 , H04N19/132 , H04N19/152 , H04N19/176 , H04N19/61
摘要： Method, apparatus and computer program product are disclosed for selectively reducing the bandwidth of real-time video data for transmission on a bus having varying bandwidth, while minimizing perceptible loss of picture quality. After detecting an overflow condition within a buffer coupled to a bus, video data to be written to the buffer is discarded until a prior pending request for transmission of a pending block of video data from the buffer is granted and begun. After beginning the transmitting, the discarding of data is discontinued and new video data is written into the buffer. A next bus request is made for transmission of all remaining data in the buffer stored prior to detecting the overflow condition. The amount of discarded data in the line is monitored and used to determine an address for a new block of data stored after the discontinuity in the line of video data. Temporal redundancies between frames of a video image is employed to fill in the discontinuity in the line of video data by using correspondingly positioned data in a corresponding line of a prior frame or field.
摘要翻译：公开了方法，装置和计算机程序产品，用于选择性地降低实时视频数据的带宽，以便在具有变化带宽的总线上进行传输，同时最小化图像质量的可察觉的损失。在检测到耦合到总线的缓冲器中的溢出状况之后，将要写入缓冲器的视频数据被丢弃，直到从缓冲器发送待处理的视频数据块的先前未决请求被授予并开始。开始发送后，中断数据的丢弃，将新的视频数据写入缓冲器。在检测到溢出条件之前，下一个总线请求用于传送所存储的缓冲器中的所有剩余数据。对该行中丢弃的数据量进行监视并用于确定在视频数据行中不连续之后存储的新数据块的地址。采用视频图像帧之间的时间冗余来通过使用相应定位的数据在先前帧或场的相应行中来填补视频数据行中的不连续性。

9. 发明授权

US06784893B2 Raster operation unit 有权
标题翻译：光栅操作单元
公开(公告)号：US06784893B2
公开(公告)日：2004-08-31
申请号：US10056318
申请日：2002-01-22
申请人： Charles F. Marino
发明人： Charles F. Marino
IPC分类号： G09G537
CPC分类号： G06F9/30029 , G06F9/30018 , G09G5/02 , G09G5/363
摘要： A method, graphics engine boolean logic unit and digital video system that provide a raster operation unit capable of providing a raster and non-raster operation function(s) is provided. The raster operation may simultaneously conduct a raster function and non-raster operation function(s) by modification of at least one of a rasterop code and a pattern operand. The invention saves considerable logic since different functions are no longer executed separately and then multiplexed.
摘要翻译：提供了一种提供能够提供光栅和非光栅操作功能的光栅操作单元的方法，图形引擎布尔逻辑单元和数字视频系统。光栅操作可以通过修改光栅代码和图案操作数中的至少一个来同时进行光栅功能和非光栅操作功能。本发明节省了相当多的逻辑，因为不同的功能不再单独执行然后被多路复用。

10. 发明授权

US5986714A Method, apparatus and computer program product for selectively reducing bandwidth of real-time video data 失效
标题翻译：用于选择性地降低实时视频数据带宽的方法和装置
公开(公告)号：US5986714A
公开(公告)日：1999-11-16
申请号：US872573
申请日：1997-06-10
申请人： Charles F. Marino
发明人： Charles F. Marino
IPC分类号： H04B1/66 , H04N7/12 , H04N7/26 , H04N7/32
CPC分类号： H04N19/423 , H04N19/132 , H04N19/152 , H04N19/176 , H04N19/61
摘要： Method, apparatus and computer program product are disclosed for selectively reducing the bandwidth of real-time video data for transmission on a bus having varying bandwidth, while minimizing perceptible loss of picture quality. After detecting an overflow condition within a buffer coupled to a bus, video data to be written to the buffer is discarded until a prior pending request for transmission of a pending block of video data from the buffer is granted and begun. After beginning the transmitting, the discarding of data is discontinued and new video data is written into the buffer. A next bus request is made for transmission of all remaining data in the buffer stored prior to detecting the overflow condition. The amount of discarded data in the line is monitored and used to determine an address for a new block of data stored after the discontinuity in the line of video data. Temporal redundancies between frames of a video image is employed to fill in the discontinuity in the line of video data by using correspondingly positioned data in a corresponding line of a prior frame or field.
摘要翻译：公开了方法，装置和计算机程序产品，用于选择性地降低实时视频数据的带宽，以便在具有变化带宽的总线上进行传输，同时最小化图像质量的可察觉的损失。在检测到耦合到总线的缓冲器中的溢出状况之后，将要写入缓冲器的视频数据被丢弃，直到从缓冲器发送待处理的视频数据块的先前未决请求被授予并开始。开始发送后，中断数据的丢弃，将新的视频数据写入缓冲器。在检测到溢出条件之前，下一个总线请求用于传送所存储的缓冲器中的所有剩余数据。对该行中丢弃的数据量进行监视并用于确定在视频数据行中不连续之后存储的新数据块的地址。采用视频图像帧之间的时间冗余来通过使用相应定位的数据在先前帧或场的相应行中来填补视频数据行中的不连续性。

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