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    • 2. 发明申请
    • Receiver with Asynchronous and Synchronous Demodulator
    • 具有异步和同步解调器的接收器
    • US20130083869A1
    • 2013-04-04
    • US13595949
    • 2012-08-27
    • Hendricus de RuijterWentao Li
    • Hendricus de RuijterWentao Li
    • H04L27/22H04B1/16
    • H04L27/22H04B1/001
    • A receiver circuit includes an asynchronous demodulator having a demodulator input to receive a first signal and a demodulator output configured to provide a demodulated signal. The receiver circuit further includes a circuit, a multiplexer, and a synchronous demodulator. The modulator circuit includes a modulator input coupled to the demodulator output and includes a modulator output. The modulator re-modulates the demodulated signal to produce a second signal and provides the second signal to the modulator output. The multiplexer includes a first input to receive the first signal, a second input coupled to the modulator output to receive the second signal, a control input to a receive a select signal, and a multiplexer output. The synchronous demodulator includes an input coupled to the multiplexer output and an output to provide a demodulated output signal corresponding to a selected one of the first signal and the second signal.
    • 接收机电路包括具有用于接收第一信号的解调器输入和被配置为提供解调信号的解调器输出的异步解调器。 接收器电路还包括电路,多路复用器和同步解调器。 调制器电路包括耦合到解调器输出并包括调制器输出的调制器输入。 调制器重调制解调信号以产生第二信号,并将第二信号提供给调制器输出。 复用器包括用于接收第一信号的第一输入端,耦合到调制器输出以接收第二信号的第二输入,接收选择信号的控制输入和多路复用器输出。 同步解调器包括耦合到多路复用器输出的输入和输出,以提供对应于第一信号和第二信号中选定的一个的解调输出信号。
    • 5. 发明授权
    • Receiver with asynchronous and synchronous demodulator
    • 具有异步和同步解调器的接收器
    • US08634502B2
    • 2014-01-21
    • US13595949
    • 2012-08-27
    • Hendricus de RuijterWentao Li
    • Hendricus de RuijterWentao Li
    • H03K9/00H04L27/00
    • H04L27/22H04B1/001
    • A receiver circuit includes an asynchronous demodulator having a demodulator input to receive a first signal and a demodulator output configured to provide a demodulated signal. The receiver circuit further includes a circuit, a multiplexer, and a synchronous demodulator. The modulator circuit includes a modulator input coupled to the demodulator output and includes a modulator output. The modulator re-modulates the demodulated signal to produce a second signal and provides the second signal to the modulator output. The multiplexer includes a first input to receive the first signal, a second input coupled to the modulator output to receive the second signal, a control input to a receive a select signal, and a multiplexer output. The synchronous demodulator includes an input coupled to the multiplexer output and an output to provide a demodulated output signal corresponding to a selected one of the first signal and the second signal.
    • 接收机电路包括具有用于接收第一信号的解调器输入和被配置为提供解调信号的解调器输出的异步解调器。 接收器电路还包括电路,多路复用器和同步解调器。 调制器电路包括耦合到解调器输出并包括调制器输出的调制器输入。 调制器重调制解调信号以产生第二信号,并将第二信号提供给调制器输出。 复用器包括用于接收第一信号的第一输入端,耦合到调制器输出以接收第二信号的第二输入,接收选择信号的控制输入和多路复用器输出。 同步解调器包括耦合到多路复用器输出的输入和输出,以提供对应于第一信号和第二信号中选定的一个的解调输出信号。
    • 7. 发明授权
    • Systems and methods for handling data rate changes within a packet or frame
    • 用于处理数据包或帧内数据速率变化的系统和方法
    • US08699630B2
    • 2014-04-15
    • US12913080
    • 2010-10-27
    • Hendricus de Ruijter
    • Hendricus de Ruijter
    • H04L27/06
    • H04L25/0262H04L27/14
    • Systems and methods for handling data rate changes within a packet or frame are described. In an embodiment, a system may include a radio frequency (RF) circuit operable to receive a message having a plurality of segments, including a first segment that is modulated according to a first modulation data rate. The system may also include a demodulator circuit coupled to the RF circuit and operable to demodulate the first segment into a first demodulated segment having a demodulation data rate, wherein the demodulation data rate is greater than the first modulation data rate. The system may further include a de-mapper circuit coupled to the demodulator circuit and operable to convert the first demodulated segment into a first converted segment having the first modulation data rate.
    • 描述用于处理分组或帧内的数据速率变化的系统和方法。 在一个实施例中,系统可以包括射频(RF)电路,其可操作以接收具有多个段的消息,包括根据第一调制数据速率调制的第一段。 该系统还可以包括耦合到RF电路并且可操作以将第一段解调成具有解调数据速率的第一解调段的解调器电路,其中解调数据速率大于第一调制数据速率。 该系统还可以包括耦合到解调器电路并且可操作以将第一解调片段转换为具有第一调制数据速率的第一转换片段的解映射器电路。
    • 10. 发明申请
    • Apparatus and Method for Interference Management
    • 干扰管理装置与方法
    • US20120329415A1
    • 2012-12-27
    • US13170172
    • 2011-06-27
    • Hendricus de Ruijter
    • Hendricus de Ruijter
    • H04B17/00
    • H03G3/3052H03G3/3078H04B1/1027H04B17/345
    • A circuit includes a front-end circuit having an input for receiving a radio frequency signal, a control input, and an output. The front-end circuit includes an adjustable gain. The circuit further includes a received signal strength indicator (RSSI) circuit including an input coupled to the output of the front-end circuit and including an output. The circuit also includes a control circuit including an input coupled to the output of the RSSI circuit and an output coupled to the control input of the front-end circuit. The control circuit is configured to iteratively adjust the adjustable gain by a pre-determined adjustment until a difference between a first RSSI measurement and a second RSSI measurement is less than or approximately equal to the pre-determined adjustment.
    • 电路包括具有用于接收射频信号的输入端,控制输入端和输出端的前端电路。 前端电路包括可调增益。 电路还包括接收信号强度指示器(RSSI)电路,其包括耦合到前端电路的输出并包括输出的输入。 电路还包括控制电路,其包括耦合到RSSI电路的输出的输入端和耦合到前端电路的控制输入的输出。 控制电路被配置为通过预定的调整来迭代地调节可调增益,直到第一RSSI测量和第二RSSI测量之间的差小于或近似等于预定的调整。