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1. 发明授权

US07899641B2 Testable electronic circuit 失效
标题翻译：可测电子线路
公开(公告)号：US07899641B2
公开(公告)日：2011-03-01
申请号：US11815313
申请日：2006-01-31
申请人： Hervé Fleury , Jean-Marc Yannou
发明人： Hervé Fleury , Jean-Marc Yannou
IPC分类号： G01R31/00
CPC分类号： G01R31/318552 , G01R31/31727
摘要： An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c). The test control circuit (16) is coupled to control the clock multiplexing circuit (15a-c, 18) dependent on the mode assumed by the test control circuit (16). The clock multiplexing circuit (15a-c, 18) is arranged to substitute clock signals from respective ones of the data terminals (11a-c) temporarily at the clock inputs of respective ones of the groups (12a-c) in the test normal mode.
摘要翻译：电子电路包括耦合到电路的数据端子（11a-c）和功能电路（10）的触发器组（12a-c）。每组（12a-c）都有一个时钟输入，用于对该组的触发器进行计时。每个组（12a-c）可以在移位配置和功能配置之间切换，用于从数据终端串行地移动测试数据，并且并行地向功能电路（10）提供信号和/或从功能电路功能电路（10）。测试控制电路（16）可以在功能模式，测试移位模式和测试正常模式之间切换。测试控制电路（16）耦合到触发器组（12a-c），以将功能模式中的功能配置和测试移位模式中的移位配置切换到功能模式。时钟多路复用电路（15a-c，18）具有耦合到数据终端（11a-c）的输入和耦合到组（12a-c）的时钟输入的输出。测试控制电路（16）被耦合以根据由测试控制电路（16）假设的模式来控制时钟复用电路（15a-c，18）。时钟多路复用电路（15a-c，18）被配置为在测试正常模式下，在各个组（12a-c）的时钟输入端临时替代来自数据终端（11a-c）中的相应数据终端的时钟信号。

2. 发明授权

US07519496B2 Electronic circuit comprising a secret sub-module 有权
标题翻译：电子电路包括秘密子模块
公开(公告)号：US07519496B2
公开(公告)日：2009-04-14
申请号：US10571834
申请日：2004-09-10
申请人： Jean-Marc Yannou , Hervé Fleury , Hervé Vincent
发明人： Jean-Marc Yannou , Hervé Fleury , Hervé Vincent
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/31719 , G01R31/318541 , G01R31/318555
摘要： The invention relates to an electronic circuit including a sub-module assembly (2) connected to the rest of the circuit, the sub-module assembly including a secret sub-module (4) for performing a function, scan chains; a built-in self test circuit including a pattern generator (5) to apply input signals to the scan chains, and a signature register (6) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.
摘要翻译：本发明涉及一种包括连接到电路的其余部分的子模块组件（2）的电子电路，子模块组件包括用于执行功能的秘密子模块（4），扫描链; 包括用于向扫描链施加输入信号的模式发生器（5）的内置自检电路和用于检查来自扫描链的输出信号的签名寄存器（6）。为了保持子模块的秘密，扫描链不连接到电路的其余部分。

3. 发明授权

US08327205B2 IC testing methods and apparatus 有权
标题翻译： IC测试方法和仪器
公开(公告)号：US08327205B2
公开(公告)日：2012-12-04
申请号：US12160211
申请日：2007-01-04
申请人： Tom Waayers , Johan C. Meirlevede , David P. Price , Norbert Schomann , Ruediger Solbach , Hervé Fleury , Jozef R. Poels
发明人： Tom Waayers , Johan C. Meirlevede , David P. Price , Norbert Schomann , Ruediger Solbach , Hervé Fleury , Jozef R. Poels
IPC分类号： G01R31/28
CPC分类号： G01R31/31858
摘要： A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK). Clocking hardware is also provided, and these provide at-speed testing which enables on the fly switching between a relatively slow tester driven clock for the shift modes and faster clocks generated by on-chip PLLs and divider circuits for the test mode.
摘要翻译：提供了一种用于测试包括多个核心的集成电路的方法，其中至少两个核心具有不同频率的不同关联的第一和第二时钟信号。使用以测试频率（TCK）计时的时钟扫描链提供测试信号。在时钟电路复位信号（clockdiv_rst）中提供转换，该时钟电路复位信号（clockdiv_rst）触发从集成的内部时钟（40）导出第一和第二时钟信号（clk_xx，clk_yy，clk_zz）的时钟分频器电路（44）的操作，电路。因此，第一和第二时钟信号基本相同地开始，并且这些在测试模式期间用于执行集成电路的测试。测试后，使用以测试频率（TCK）计时的时钟扫描链输出测试结果。还提供了时钟硬件，并且这些提供了高速测试，这使得能够在用于移位模式的相对较慢的测试器驱动时钟和由片上PLL产生的更快时钟和用于测试模式的分频器电路之间进行快速切换。

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