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1. 发明申请

US20110180897A1 PACKAGED SEMICONDUCTOR PRODUCT AND METHOD FOR MANUFACTURE THEREOF 有权
标题翻译：包装半导体产品及其制造方法
公开(公告)号：US20110180897A1
公开(公告)日：2011-07-28
申请号：US13001391
申请日：2009-06-26
申请人： Eric Pieraerts , Jean-Marc Yannou , Stephane Bellenger , Mickael Pommier
发明人： Eric Pieraerts , Jean-Marc Yannou , Stephane Bellenger , Mickael Pommier
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L23/3107 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/3171 , H01L23/3185 , H01L24/19 , H01L2224/04105 , H01L2224/20 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041
摘要： Packaged semiconductor product (2) including a first semiconductor device (4A) and a packaging structure with a protective envelope (6) and a first and second external electrode (8,10). The first semiconductor device (4A) has a first substrate (11A) and is provided with a first passivation layer (12A) and a first electronic structure. The first substrate has a first main surface (14). The first substrate (11A) is embedded in the protective envelope (6) and the first main surface (14) faces a first opening (23) of the protective envelope (6). The first electronic structure has a first and a second contact region (20, 22) for electrically contacting the first electronic structure. The first passivation layer (12A) substantially covers the first main surface (14) and the first electronic structure. The protective envelope (6) extends between the first passivation layer (12A) and the first external electrode (8) towards the first contact region (20).
摘要翻译：封装半导体产品（2）包括第一半导体器件（4A）和具有保护外壳（6）和第一和第二外部电极（8,10）的封装结构。第一半导体器件（4A）具有第一衬底（11A）并且设置有第一钝化层（12A）和第一电子结构。第一基板具有第一主表面（14）。第一基板（11A）嵌入保护外壳（6）中，第一主表面（14）面向保护外壳（6）的第一开口（23）。第一电子结构具有用于电接触第一电子结构的第一和第二接触区域（20,22）。第一钝化层（12A）基本上覆盖第一主表面（14）和第一电子结构。保护外壳（6）朝着第一接触区域（20）在第一钝化层（12A）和第一外部电极（8）之间延伸。

2. 发明授权

US07899641B2 Testable electronic circuit 失效
标题翻译：可测电子线路
公开(公告)号：US07899641B2
公开(公告)日：2011-03-01
申请号：US11815313
申请日：2006-01-31
申请人： Hervé Fleury , Jean-Marc Yannou
发明人： Hervé Fleury , Jean-Marc Yannou
IPC分类号： G01R31/00
CPC分类号： G01R31/318552 , G01R31/31727
摘要： An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c). The test control circuit (16) is coupled to control the clock multiplexing circuit (15a-c, 18) dependent on the mode assumed by the test control circuit (16). The clock multiplexing circuit (15a-c, 18) is arranged to substitute clock signals from respective ones of the data terminals (11a-c) temporarily at the clock inputs of respective ones of the groups (12a-c) in the test normal mode.
摘要翻译：电子电路包括耦合到电路的数据端子（11a-c）和功能电路（10）的触发器组（12a-c）。每组（12a-c）都有一个时钟输入，用于对该组的触发器进行计时。每个组（12a-c）可以在移位配置和功能配置之间切换，用于从数据终端串行地移动测试数据，并且并行地向功能电路（10）提供信号和/或从功能电路功能电路（10）。测试控制电路（16）可以在功能模式，测试移位模式和测试正常模式之间切换。测试控制电路（16）耦合到触发器组（12a-c），以将功能模式中的功能配置和测试移位模式中的移位配置切换到功能模式。时钟多路复用电路（15a-c，18）具有耦合到数据终端（11a-c）的输入和耦合到组（12a-c）的时钟输入的输出。测试控制电路（16）被耦合以根据由测试控制电路（16）假设的模式来控制时钟复用电路（15a-c，18）。时钟多路复用电路（15a-c，18）被配置为在测试正常模式下，在各个组（12a-c）的时钟输入端临时替代来自数据终端（11a-c）中的相应数据终端的时钟信号。

3. 发明授权

US07519494B2 Integrated circuit with signature computation 有权
标题翻译：具有签名计算的集成电路
公开(公告)号：US07519494B2
公开(公告)日：2009-04-14
申请号：US10569721
申请日：2004-08-26
申请人： Stéphane Briere , Jean-Marc Yannou , Delphine Rivasseau
发明人： Stéphane Briere , Jean-Marc Yannou , Delphine Rivasseau
IPC分类号： G01R31/00
CPC分类号： G01R31/318547 , H04N17/004 , H04N17/04
摘要： The present invention relates to an integrated circuit (DEC V) for processing a plurality of data samples (P) of a data signal (I), wherein said integrated circuit is associated with a counter (CT) and comprises means (SIGN M) for computing a signature, said counter (CT) being adapted to trigger and stop a computation of a signature of said data signal (I), said signature being recalculated each time a data sample (P) of said data signal is output by said integrated circuit (DEC V). Use: Video decoder in a set-top-box.
摘要翻译：本发明涉及一种用于处理数据信号（I）的多个数据样本（P）的集成电路（DEC V），其中所述集成电路与计数器（CT）相关联，并且包括：装置（SIGN M），用于计算签名，所述计数器（CT）适于触发和停止所述数据信号（I）的签名的计算，每当所述数据信号的数据样本（P）由所述集成电路输出时，所述签名被重新计算（DEC V）。使用：视频解码器在机顶盒中。

4. 发明授权

US08541865B2 Semiconductor device with improved ESD protection 有权
标题翻译：具有改进的ESD保护的半导体器件
公开(公告)号：US08541865B2
公开(公告)日：2013-09-24
申请号：US12739333
申请日：2008-10-22
申请人： Jean-Marc Yannou , Johannes Van Zwol , Emmanuel Savin
发明人： Jean-Marc Yannou , Johannes Van Zwol , Emmanuel Savin
IPC分类号： H01L29/866 , H01L21/762
CPC分类号： H01L23/60 , H01L23/481 , H01L25/167 , H01L27/0255 , H01L27/0814 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/13024 , H01L2224/131 , H01L2924/3011 , H01L2924/00014
摘要： The present invention relates to a semiconductor device, comprising a semiconductor substrate (102) with a thickness of less than 100 micrometer and with a first substrate side and an opposite second substrate side. A plurality of at least four monolithically integrated Zener or avalanche diodes (164,166,168,170) with a reverse breakdown voltage of less than 20 V are defined in the semiconductor substrate and connected with each other in a series connection. The diodes are defined in a plurality of mutually isolated substrate islands (120,122,124,126) in the semiconductor substrate, at least one diode per substrate island. The substrate islands are laterally surrounded by through-substrate isolations extending from the first to the second substrate side and comprising a filling (128) that electrically isolates a respective substrate island from a respective laterally surrounding area of the semiconductor substrate.
摘要翻译：本发明涉及一种半导体器件，包括厚度小于100微米的半导体衬底（102），并具有第一衬底侧和相对的第二衬底侧。多个至少四个具有小于20V的反向击穿电压的齐纳二极管或雪崩二极管（164,166,168,170）被限定在半导体衬底中并以串联方式彼此连接。二极管限定在半导体衬底中的多个相互隔离的衬底岛（120,122,124,126）中，每个衬底岛至少有一个二极管。衬底岛被从第一衬底侧延伸到第二衬底侧的贯穿衬底隔离件横向包围，并且包括将相应衬底岛与半导体衬底的相应横向周围区域电隔离的填充物（128）。

5. 发明申请

US20110121425A1 SEMICONDUCTOR DEVICE WITH IMPROVED ESD PROTECTION 有权
标题翻译：具有改进的ESD保护的半导体器件
公开(公告)号：US20110121425A1
公开(公告)日：2011-05-26
申请号：US12739333
申请日：2008-10-22
申请人： Jean-Marc Yannou , Johannes Van Zwol , Emmanuel Savin
发明人： Jean-Marc Yannou , Johannes Van Zwol , Emmanuel Savin
IPC分类号： H01L29/866 , H01L21/762
CPC分类号： H01L23/60 , H01L23/481 , H01L25/167 , H01L27/0255 , H01L27/0814 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/13024 , H01L2224/131 , H01L2924/3011 , H01L2924/00014
摘要： The present invention relates to a semiconductor device, comprising a semiconductor substrate (102) with a thickness of less than 100 micrometer and with a first substrate side and an opposite second substrate side. A plurality of at least four monolithically integrated Zener or avalanche diodes (164,166,168,170) with a reverse breakdown voltage of less than 20 V are defined in the semiconductor substrate and connected with each other in a series connection. The diodes are defined in a plurality of mutually isolated substrate islands (120,122,124,126) in the semiconductor substrate, at least one diode per substrate island. The substrate islands are laterally surrounded by through-substrate isolations extending from the first to the second substrate side and comprising a filling (128) that electrically isolates a respective substrate island from a respective laterally surrounding area of the semiconductor substrate.
摘要翻译：本发明涉及一种半导体器件，包括厚度小于100微米的半导体衬底（102），并具有第一衬底侧和相对的第二衬底侧。多个至少四个具有小于20V的反向击穿电压的齐纳二极管或雪崩二极管（164,166,168,170）被限定在半导体衬底中并以串联方式彼此连接。二极管限定在半导体衬底中的多个相互隔离的衬底岛（120,122,124,126）中，每个衬底岛至少有一个二极管。衬底岛被从第一衬底侧延伸到第二衬底侧的贯穿衬底隔离件横向包围，并且包括将相应衬底岛与半导体衬底的相应横向周围区域电隔离的填充物（128）。

6. 发明申请

US20080185614A1 Integrated Circuit Assembly with Passive Integration Substrate for Power and Ground Line Routing on Top of an Integrated Circuit Chip 有权
标题翻译：集成电路组件与集成电路芯片顶部的电源和地线路由无源集成基板
公开(公告)号：US20080185614A1
公开(公告)日：2008-08-07
申请号：US11912843
申请日：2006-04-26
申请人： Patrice Gamand , Jean-Marc Yannou , Fabrice Verjus , Cyrille Cathelin
发明人： Patrice Gamand , Jean-Marc Yannou , Fabrice Verjus , Cyrille Cathelin
IPC分类号： H01L27/10
CPC分类号： H01L25/16 , H01L23/49833 , H01L23/50 , H01L24/48 , H01L2224/05554 , H01L2224/16145 , H01L2224/16225 , H01L2224/16265 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/14 , H01L2924/19011 , H01L2924/19104 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit assembly (ICA) comprises: a digital and/or analog integrated circuit (S1) having a core with input and/or output pins and at least one power supply connection pad (PP) and one ground connection pad (GP) connected to a chosen one of the input and/or output pins and respectively connected to power supply and ground connection zones (MZ1) of a printed circuit board (PCB), and a passive integration substrate (S2) set on top of the digital and/or analog integrated circuit (S1) and comprising i) at least first and second input zones respectively connected to the ground (GP) and power supply (PP) connection pads to, be fed with input ground and supply voltages, ii) input and/or output zones connected to chosen core input and/or output pins, and Ëi) a passive integrated circuit (PIC) connected to the first and second input zones and arranged to feed the substrate input and/or output zones with chosen ground and supply voltages defined from the input ground and supply voltages.
摘要翻译：集成电路组件（ICA）包括：数字和/或模拟集成电路（S1），其具有带有输入和/或输出引脚的核心和至少一个电源连接焊盘（PP）和一个接地连接焊盘（GP）连接到所选择的输入和/或输出引脚中的一个并分别连接到印刷电路板（PCB）的电源和接地连接区（MZ 1），以及设置在印刷电路板（PCB）顶部的无源集成基板（S 2）数字和/或模拟集成电路（S1），并且包括i）分别连接到地（GP）和电源（PP）连接焊盘的至少第一和第二输入区域，被馈送输入接地和电源电压，ii ）连接到所选择的核心输入和/或输出引脚的输入和/或输出区域，以及Ëi连接到所述第一和第二输入区域的无源集成电路（PIC），并且被布置为将所选择的所述基板输入和/或输出区域接地和电源电压从输入地和su定义提供电压。

7. 发明授权

US08963314B2 Packaged semiconductor product and method for manufacture thereof 有权
标题翻译：封装半导体产品及其制造方法
公开(公告)号：US08963314B2
公开(公告)日：2015-02-24
申请号：US13001391
申请日：2009-06-26
申请人： Eric Pieraerts , Jean-Marc Yannou , Stephane Bellenger , Mickael Pommier
发明人： Eric Pieraerts , Jean-Marc Yannou , Stephane Bellenger , Mickael Pommier
IPC分类号： H01L23/48 , H01L23/31 , H01L21/56 , H01L23/00
CPC分类号： H01L23/3107 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/3171 , H01L23/3185 , H01L24/19 , H01L2224/04105 , H01L2224/20 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041
摘要： Packaged semiconductor product (2) including a first semiconductor device (4A) and a packaging structure with a protective envelope (6) and a first and second external electrode (8,10). The first semiconductor device (4A) has a first substrate (11A) and is provided with a first passivation layer (12A) and a first electronic structure. The first substrate has a first main surface (14). The first substrate (11A) is embedded in the protective envelope (6) and the first main surface (14) faces a first opening (23) of the protective envelope (6). The first electronic structure has a first and a second contact region (20, 22) for electrically contacting the first electronic structure. The first passivation layer (12A) substantially covers the first main surface (14) and the first electronic structure. The protective envelope (6) extends between the first passivation layer (12A) and the first external electrode (8) towards the first contact region (20).
摘要翻译：封装半导体产品（2）包括第一半导体器件（4A）和具有保护外壳（6）和第一和第二外部电极（8,10）的封装结构。第一半导体器件（4A）具有第一衬底（11A）并且设置有第一钝化层（12A）和第一电子结构。第一基板具有第一主表面（14）。第一基板（11A）嵌入保护外壳（6）中，第一主表面（14）面向保护外壳（6）的第一开口（23）。第一电子结构具有用于电接触第一电子结构的第一和第二接触区域（20,22）。第一钝化层（12A）基本上覆盖第一主表面（14）和第一电子结构。保护外壳（6）朝着第一接触区域（20）在第一钝化层（12A）和第一外部电极（8）之间延伸。

8. 发明授权

US08178901B2 Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip 有权
标题翻译：集成电路组件，具有无源集成基板，用于集成电路芯片顶部的电源和接地线路由
公开(公告)号：US08178901B2
公开(公告)日：2012-05-15
申请号：US11912843
申请日：2006-04-26
申请人： Patrice Gamand , Jean-Marc Yannou , Fabrice Verjus , Cyrille Cathelin
发明人： Patrice Gamand , Jean-Marc Yannou , Fabrice Verjus , Cyrille Cathelin
IPC分类号： H01L27/00
CPC分类号： H01L25/16 , H01L23/49833 , H01L23/50 , H01L24/48 , H01L2224/05554 , H01L2224/16145 , H01L2224/16225 , H01L2224/16265 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/14 , H01L2924/19011 , H01L2924/19104 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit assembly (ICA) comprises: a digital and/or analog integrated circuit (S1) having a core with input and/or output pins and at least one power supply connection pad (PP) and one ground connection pad (GP) connected to a chosen one of the input and/or output pins and respectively connected to power supply and ground connection zones (MZ1) of a printed circuit board (PCB), and a passive integration substrate (S2) set on top of the digital and/or analog integrated circuit (S1) and comprising i) at least first and second input zones respectively connected to the ground (GP) and power supply (PP) connection pads to be fed with input ground and supply voltages, ii) input and/or output zones connected to chosen core input and/or output pins, and Ëi) a passive integrated circuit (PIC) connected to the first and second input zones and arranged to feed the substrate input and/or output zones with chosen ground and supply voltages defined from the input ground and supply voltages.
摘要翻译：集成电路组件（ICA）包括：数字和/或模拟集成电路（S1），其具有带有输入和/或输出引脚的核心，以及连接至少一个电源连接焊盘（PP）和一个接地连接焊盘（GP）分别连接到印刷电路板（PCB）的电源和接地连接区域（MZ1）中的所选择的一个输入和/或输出引脚以及设置在数字和/或输出引脚上的无源集成基板（S2）或模拟集成电路（S1），并且包括i）分别连接到接地（GP）和电源（PP）连接焊盘的至少第一和第二输入区域，以供给输入的接地和电源电压; ii）输入和/或输出区域，连接到所选择的核心输入和/或输出引脚，以及Ëi）连接到第一和第二输入区域的无源集成电路（PIC），并且被布置为馈送所选择的接地和电源电压的基板输入和/或输出区域从输入接地和电源电压年龄

9. 发明申请

US20100044853A1 SYSTEM-IN-PACKAGE WITH THROUGH SUBSTRATE VIA HOLES 审中-公开
标题翻译：通过底座的系统包装
公开(公告)号：US20100044853A1
公开(公告)日：2010-02-25
申请号：US12523053
申请日：2008-01-14
申请人： Ronald Dekker , Jean-Marc Yannou , Nicolaas J. A. Van Veen
发明人： Ronald Dekker , Jean-Marc Yannou , Nicolaas J. A. Van Veen
IPC分类号： H01L23/538 , H01L21/50 , H05K1/11
CPC分类号： H01L23/49827 , B81C1/00087 , B81C1/00238 , H01L23/13 , H01L23/481 , H01L23/49833 , H01L25/0657 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06572 , H01L2924/00014 , H01L2924/1461 , H01L2924/3011 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： The present invention relates to a system-in-package that comprises an integration substrate with a thickness of less than 100 micrometer and a plurality of through-substrate vias, which have an aspect ratio larger than 5. A first chip is attached to the integration substrate and arranged between the integration substrate and a support, which is suitable for mechanically supporting the integration substrate during processing and handling. The system-in-package can be fabricated according to the invention without a through-substrate-hole etching step. The large aspect ratio implies reduced lateral extensions, which allow increasing the integration density and decreasing lead inductances.
摘要翻译：本发明涉及一种包括厚度小于100微米的整合衬底和多个贯穿衬底通孔的系统级封装，其具有大于5的长宽比。第一芯片附接到集成基板并且布置在整合基板和支撑件之间，该支撑件适用于在加工和处理期间机械地支撑整合基板。根据本发明，可以制造系统级封装，而无需通过基板孔蚀刻步骤。大的纵横比意味着减小的横向延伸，这允许增加积分密度并减少引线电感。

10. 发明授权

US07519496B2 Electronic circuit comprising a secret sub-module 有权
标题翻译：电子电路包括秘密子模块
公开(公告)号：US07519496B2
公开(公告)日：2009-04-14
申请号：US10571834
申请日：2004-09-10
申请人： Jean-Marc Yannou , Hervé Fleury , Hervé Vincent
发明人： Jean-Marc Yannou , Hervé Fleury , Hervé Vincent
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/31719 , G01R31/318541 , G01R31/318555
摘要： The invention relates to an electronic circuit including a sub-module assembly (2) connected to the rest of the circuit, the sub-module assembly including a secret sub-module (4) for performing a function, scan chains; a built-in self test circuit including a pattern generator (5) to apply input signals to the scan chains, and a signature register (6) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.
摘要翻译：本发明涉及一种包括连接到电路的其余部分的子模块组件（2）的电子电路，子模块组件包括用于执行功能的秘密子模块（4），扫描链; 包括用于向扫描链施加输入信号的模式发生器（5）的内置自检电路和用于检查来自扫描链的输出信号的签名寄存器（6）。为了保持子模块的秘密，扫描链不连接到电路的其余部分。

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