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1. 发明授权

US08098523B2 Semiconductor memory device with memory cell having charge accumulation layer and control gate and memory system 有权
标题翻译：具有存储单元的半导体存储器件具有电荷累积层和控制栅极和存储器系统
公开(公告)号：US08098523B2
公开(公告)日：2012-01-17
申请号：US12831689
申请日：2010-07-07
申请人： Hidetaka Tsuji , Tomoji Takada
发明人： Hidetaka Tsuji , Tomoji Takada
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G06F12/0246 , G11C11/5621 , G11C16/0483 , G11C16/34 , G11C2211/5641
摘要： A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2i, where i is a natural number and M is a natural number greater than or equal to 3) of data. The memory block includes the first memory cell transistors and is erase unit of the data. The data held in the first memory cell transistors included in the memory block is erased simultaneously. The size of data the memory block is capable of holding is L bits (L=2k, where k is a natural number). The word lines connect in common the control gates of the first memory cell transistors.
摘要翻译：半导体存储器件包括第一存储单元晶体管，存储块和字线。每个第一存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且能够保持M位（M≠2i，其中i是自然数，M是大于或等于3的自然数））数据的。存储块包括第一存储单元晶体管，并且是数据的擦除单元。包含在存储块中的第一存储单元晶体管中保存的数据被同时擦除。存储器块能够保持的数据的大小是L位（L = 2k，其中k是自然数）。字线共同连接第一存储单元晶体管的控制栅极。

2. 发明授权

US07773417B2 Semiconductor memory device with memory cell having charge accumulation layer and control gate and memory system 有权
标题翻译：具有存储单元的半导体存储器件具有电荷累积层和控制栅极和存储器系统
公开(公告)号：US07773417B2
公开(公告)日：2010-08-10
申请号：US12166909
申请日：2008-07-02
申请人： Hidetaka Tsuji , Tomoji Takada
发明人： Hidetaka Tsuji , Tomoji Takada
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G06F12/0246 , G11C11/5621 , G11C16/0483 , G11C16/34 , G11C2211/5641
摘要： A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2i, where i is a natural number and M is a natural number greater than or equal to 3) of data. The memory block includes the first memory cell transistors and is erase unit of the data. The data held in the first memory cell transistors included in the memory block is erased simultaneously. The size of data the memory block is capable of holding is L bits (L=2k, where k is a natural number). The word lines connect in common the control gates of the first memory cell transistors.
摘要翻译：半导体存储器件包括第一存储单元晶体管，存储块和字线。每个第一存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且能够保持M位（M≠2i，其中i是自然数，M是大于或等于3的自然数））数据的。存储块包括第一存储单元晶体管，并且是数据的擦除单元。包含在存储块中的第一存储单元晶体管中保存的数据被同时擦除。存储器块能够保持的数据的大小是L位（L = 2k，其中k是自然数）。字线共同连接第一存储单元晶体管的控制栅极。

3. 发明申请

US20100271876A1 SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND MEMORY SYSTEM 有权
标题翻译：具有存储单元的半导体存储器件具有充电累积层和控制栅和存储器系统
公开(公告)号：US20100271876A1
公开(公告)日：2010-10-28
申请号：US12831689
申请日：2010-07-07
申请人： Hidetaka TSUJI , Tomoji Takada
发明人： Hidetaka TSUJI , Tomoji Takada
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C8/12 , G06F12/0246 , G11C11/5621 , G11C16/0483 , G11C16/34 , G11C2211/5641
摘要： A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2i, where i is a natural number and M is a natural number greater than or equal to 3) of data. The memory block includes the first memory cell transistors and is erase unit of the data. The data held in the first memory cell transistors included in the memory block is erased simultaneously. The size of data the memory block is capable of holding is L bits (L=2k, where k is a natural number). The word lines connect in common the control gates of the first memory cell transistors.
摘要翻译：半导体存储器件包括第一存储单元晶体管，存储块和字线。每个第一存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且能够保持M位（M≠2i，其中i是自然数，M是大于或等于3的自然数））数据的。存储块包括第一存储单元晶体管，并且是数据的擦除单元。包含在存储块中的第一存储单元晶体管中保存的数据被同时擦除。存储器块能够保持的数据的大小是L位（L = 2k，其中k是自然数）。字线共同连接第一存储单元晶体管的控制栅极。

4. 发明授权

US08341333B2 Method of writing data into semiconductor memory and memory controller 有权
标题翻译：将数据写入半导体存储器和存储器控制器的方法
公开(公告)号：US08341333B2
公开(公告)日：2012-12-25
申请号：US12441785
申请日：2008-02-13
申请人： Tomoji Takada
发明人： Tomoji Takada
IPC分类号： G06F12/00
CPC分类号： G11C11/5628 , G11C7/1006 , G11C11/5642 , G11C16/0483 , G11C16/10
摘要： A method of writing data into a semiconductor memory (11) in which nonvolatile memory cells (MC) each having a gate connected to a word line (WL) are connected in series, the method comprising selecting (S13) a scrambling method for the data according to a word line address for memory cells (MC) into which data is to be written, scrambling (S14) the data, and writing (S15) the scrambled data into the memory cells (MC) according to the word line address. The data is scrambled using the selected scrambling method.
摘要翻译：一种将数据写入半导体存储器（11）的方法，其中每个具有连接到字线（WL）的栅极的非易失性存储器单元（MC）串联连接，所述方法包括：选择（S13）数据的加扰方法根据要写入数据的存储单元（MC）的字线地址，对数据进行加扰（S14），并根据字线地址将加扰数据写入存储单元（MC）。使用所选择的加扰方法对数据进行加扰。

5. 发明申请

US20070245098A1 METHOD FOR CONTROLLING SEMICONDUCTOR STORAGE DEVICE COMPRISING MEMORY CELLS EACH CONFIGURED TO HOLD MULTI-BIT DATA, AND MEMORY CARD PROVIDED WITH SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：用于控制每个配置保存多位数据的存储器单元的半导体存储器件的控制方法以及由半导体存储器件提供的存储器卡
公开(公告)号：US20070245098A1
公开(公告)日：2007-10-18
申请号：US11691799
申请日：2007-03-27
申请人： Tomoji Takada
发明人： Tomoji Takada
IPC分类号： G06F13/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A method for controlling a semiconductor storage device including memory cells each configured to hold data of 2 bits or more, the method includes starting first signal processing, and inputting lower bits into the semiconductor storage device in a ready state, writing the lower bits to the memory cells, changing the semiconductor storage device from the ready state into a busy state, changing the semiconductor storage device from the busy state into the ready state, and finishing the first signal processing, starting second signal processing, and inputting upper bits into the semiconductor storage device in the ready state, and writing the upper bits to the memory cells. A period for the writing the upper bits is longer than a period for the writing the lower bits. A period for performing the second signal processing is longer than a period for performing the first signal processing.
摘要翻译：一种用于控制包括存储单元的半导体存储器件的方法，每个存储器单元被配置为保持2位或更多数据的数据，该方法包括开始第一信号处理，并将低位向低位输入到准备状态的半导体存储器件中，将低位写入到存储单元，将半导体存储装置从就绪状态改变为忙状态，将半导体存储装置从繁忙状态改变为就绪状态，并且完成第一信号处理，开始第二信号处理以及将高位输入到半导体存储设备处于就绪状态，并将高位写入存储器单元。用于写入高位的周期长于写入低位的周期。用于执行第二信号处理的周期比用于执行第一信号处理的周期长。

6. 发明申请

US20090323417A1 SEMICONDUCTOR MEMORY REPAIRING A DEFECTIVE BIT AND SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：半导体存储器修复缺陷位和半导体存储器系统
公开(公告)号：US20090323417A1
公开(公告)日：2009-12-31
申请号：US12164782
申请日：2008-06-30
申请人： Tomoji Takada
发明人： Tomoji Takada
IPC分类号： G11C16/04 , G11C7/00 , G11C29/00
CPC分类号： G11C29/42 , G11C29/44 , G11C29/4401 , G11C2029/0407
摘要： A semiconductor memory has a plurality of blocks, and each of the blocks comprises a plurality of pages, and further, each of the pages has a plurality of memory cells. A block having defective bits less than N (N is an integer number more than 0) in all pages of the block stores a first data showing a normal block. A block including at least one page having defective bits more than N and including no page having defective bits more than M (M is an integer number of M>N) stores a second data showing a psedo-pass block as a pseudo-normal block. A block including at least one page having defective bits more than M stores a third data showing a defective block.
摘要翻译：半导体存储器具有多个块，并且每个块包括多个页，并且此外，每个页具有多个存储单元。在块的所有页面中具有小于N（N是大于0的整数）的缺陷位的块存储表示正常块的第一数据。包括至少一个具有比N更多的缺陷位的页面并且不包括不超过M的缺陷位的页面（M是M> N的整数）的块将存储有伪代码块的第二数据作为伪正常块。包括至少一个具有超过M的缺陷位的页面的块存储表示缺陷块的第三数据。

7. 发明授权

US4667310A Large scale circuit device containing simultaneously accessible memory cells 失效
标题翻译：包含同时存取存储单元的大规模电路装置
公开(公告)号：US4667310A
公开(公告)日：1987-05-19
申请号：US681485
申请日：1984-12-13
申请人： Tomoji Takada
发明人： Tomoji Takada
IPC分类号： G11C11/41 , G11C8/16 , G11C11/412 , G11C11/34
CPC分类号： G11C8/16
摘要： A master slice type LSI is constructed as a three port memory circuit in which respective cells exclusively utilized as memory circuits constituting respective memory regions can be accessed simultaneously. More particularly each cell exclusively used as a memory circuit is constituted by a flip-flop circuit including two inverters (31, 32) which are connected in parallel opposition, a single write data input line (39) and two read out data output lines (40, 41) which are connected to the flip-flop circuit through transfer gate circuits (33,34,35), respectively, and at least three word lines (36, 37, 38) along which independent word signals are transmitted. The three transfer gate circuits (33, 34, 35) are independently enabled and disenabled based on the word signals transmitted over the word lines (36, 37, 38).
摘要翻译：主片式LSI构成为可以同时访问专用于构成各个存储器区域的存储电路的各个单元的三端口存储电路。更具体地，专门用作存储器电路的每个单元由包括并联对置的两个反相器（31,32），单个写入数据输入线（39）和两个读出数据输出线（32）的触发器电路构成， 40,31）分别通过传输门电路（33,34,35）和至少三个字线（36,37,38）连接到触发器电路，沿着这些字线发送独立的字信号。基于通过字线（36,37,38）发送的字信号，三个传输门电路（33,34,35）独立地使能和禁用。

8. 发明授权

US08089806B2 Method for controlling semiconductor storage device comprising memory cells each configured to hold multi-bit data, and memory card provided with semiconductor storage device 有权
标题翻译：用于控制半导体存储装置的方法，包括各自被配置为保持多位数据的存储单元，以及设置有半导体存储装置的存储卡
公开(公告)号：US08089806B2
公开(公告)日：2012-01-03
申请号：US12405968
申请日：2009-03-17
申请人： Tomoji Takada
发明人： Tomoji Takada
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A method for controlling a semiconductor storage device including memory cells each configured to hold data of 2 bits or more, the method includes starting first signal processing, and inputting lower bits into the semiconductor storage device in a ready state, writing the lower bits to the memory cells, changing the semiconductor storage device from the ready state into a busy state, changing the semiconductor storage device from the busy state into the ready state, and finishing the first signal processing, starting second signal processing, and inputting upper bits into the semiconductor storage device in the ready state, and writing the upper bits to the memory cells. A period for the writing the upper bits is longer than a period for the writing the lower bits. A period for performing the second signal processing is longer than a period for performing the first signal processing.
摘要翻译：一种用于控制包括存储单元的半导体存储器件的方法，每个存储器单元被配置为保持2位或更多数据的数据，该方法包括开始第一信号处理，并将低位向低位输入到准备状态的半导体存储器件中，将低位写入到存储单元，将半导体存储装置从就绪状态改变为忙状态，将半导体存储装置从繁忙状态改变为就绪状态，并且完成第一信号处理，开始第二信号处理以及将高位输入到半导体存储设备处于就绪状态，并将高位写入存储器单元。用于写入高位的周期长于写入低位的周期。用于执行第二信号处理的周期比用于执行第一信号处理的周期长。

9. 发明授权

US07515466B2 Method for controlling semiconductor storage device comprising memory cells each configured to hold multi-bit data, and memory card provided with semiconductor storage device 有权
标题翻译：用于控制半导体存储装置的方法，包括各自被配置为保持多位数据的存储单元，以及设置有半导体存储装置的存储卡
公开(公告)号：US07515466B2
公开(公告)日：2009-04-07
申请号：US11691799
申请日：2007-03-27
申请人： Tomoji Takada
发明人： Tomoji Takada
IPC分类号： G11C11/03
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A method for controlling a semiconductor storage device including memory cells each configured to hold data of 2 bits or more, the method includes starting first signal processing, and inputting lower bits into the semiconductor storage device in a ready state, writing the lower bits to the memory cells, changing the semiconductor storage device from the ready state into a busy state, changing the semiconductor storage device from the busy state into the ready state, and finishing the first signal processing, starting second signal processing, and inputting upper bits into the semiconductor storage device in the ready state, and writing the upper bits to the memory cells. A period for the writing the upper bits is longer than a period for the writing the lower bits. A period for performing the second signal processing is longer than a period for performing the first signal processing.
摘要翻译：一种用于控制包括存储单元的半导体存储器件的方法，每个存储器单元被配置为保持2位或更多数据的数据，该方法包括开始第一信号处理，并将低位向低位输入到准备状态的半导体存储器件中，将低位写入到存储单元，将半导体存储装置从就绪状态改变为忙状态，将半导体存储装置从繁忙状态改变为就绪状态，并且完成第一信号处理，开始第二信号处理以及将高位输入到半导体存储设备处于就绪状态，并将高位写入存储器单元。用于写入高位的周期长于写入低位的周期。用于执行第二信号处理的周期比用于执行第一信号处理的周期长。

10. 发明授权

US07864578B2 Semiconductor memory repairing a defective bit and semiconductor memory system 有权
标题翻译：半导体存储器修复有缺陷的位和半导体存储器系统
公开(公告)号：US07864578B2
公开(公告)日：2011-01-04
申请号：US12164782
申请日：2008-06-30
申请人： Tomoji Takada
发明人： Tomoji Takada
IPC分类号： G11C16/04 , G11C7/00 , G11C29/00
CPC分类号： G11C29/42 , G11C29/44 , G11C29/4401 , G11C2029/0407
摘要： A semiconductor memory has a plurality of blocks, and each of the blocks comprises a plurality of pages, and further, each of the pages has a plurality of memory cells. A block having defective bits less than N (N is an integer number more than 0) in all pages of the block stores a first data showing a normal block. A block including at least one page having defective bits more than N and including no page having defective bits more than M (M is an integer number of M>N) stores a second data showing a psedo-pass block as a pseudo-normal block. A block including at least one page having defective bits more than M stores a third data showing a defective block.
摘要翻译：半导体存储器具有多个块，并且每个块包括多个页，并且此外，每个页具有多个存储单元。在块的所有页面中具有小于N（N是大于0的整数）的缺陷位的块存储表示正常块的第一数据。包括至少一个具有比N更多的缺陷位的页面并且不包括不超过M的缺陷位的页面（M是M> N的整数）的块将存储有伪代码块的第二数据作为伪正常块。包括至少一个具有超过M的缺陷位的页面的块存储表示缺陷块的第三数据。

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