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    • 1. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20090180341A1
    • 2009-07-16
    • US12314860
    • 2008-12-17
    • Akira IdeYasuhiro TakaiTomonori SekiguchiRiichiro TakemuraSatoru AkiyamaHiroaki Nakaya
    • Akira IdeYasuhiro TakaiTomonori SekiguchiRiichiro TakemuraSatoru AkiyamaHiroaki Nakaya
    • G11C7/00H03L7/06G11C8/18
    • G11C7/22G11C7/04G11C7/1048G11C7/12G11C7/20G11C7/222G11C11/4094H01L27/0207H01L27/108H01L27/10897H03K5/15066
    • Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).
    • 公开了一种半导体器件,包括第一时钟发生器,其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器,其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号,第二时钟信号,来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号,以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下,基于定时寄存器(图6)中存储的信息,定时信号以定时发生器输出。
    • 7. 发明授权
    • Timing control circuit and semiconductor storage device
    • 定时控制电路和半导体存储设备
    • US07973582B2
    • 2011-07-05
    • US12205668
    • 2008-09-05
    • Akira IdeYasuhiro TakaiTomonori SekiguchiRiichiro TakemuraSatoru AkiyamaHiroaki Nakaya
    • Akira IdeYasuhiro TakaiTomonori SekiguchiRiichiro TakemuraSatoru AkiyamaHiroaki Nakaya
    • H03H11/26
    • H03K5/15033
    • Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.
    • 公开了一种定时控制电路,其以基本相等的间隔接收具有周期T1和L个不同相位(其中L是正整数)的第二时钟的一组第一时钟,并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m·T1 + n·(T2 / L)的延迟td,其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数,并产生从第一个时钟延迟大约m·T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后,从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息,精细延迟电路产生从粗定时信号的延迟量近似为n·(T2 / L)的精细定时信号。 m和n的值可以由寄存器设置。
    • 8. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07903492B2
    • 2011-03-08
    • US12314860
    • 2008-12-17
    • Akira IdeYasuhiro TakaiTomonori SekiguchiRiichiro TakemuraSatoru AkiyamaHiroaki Nakaya
    • Akira IdeYasuhiro TakaiTomonori SekiguchiRiichiro TakemuraSatoru AkiyamaHiroaki Nakaya
    • G11C7/00
    • G11C7/22G11C7/04G11C7/1048G11C7/12G11C7/20G11C7/222G11C11/4094H01L27/0207H01L27/108H01L27/10897H03K5/15066
    • Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).
    • 公开了一种半导体器件,包括第一时钟发生器,其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器,其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号,第二时钟信号,来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号,以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下,基于定时寄存器(图6)中存储的信息,定时信号以定时发生器输出。