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1. 发明授权

US09002969B2 Distributed multimedia server system, multimedia information distribution method, and computer product 有权
标题翻译：分布式多媒体服务器系统，多媒体信息分发方法，程序及记录介质
公开(公告)号：US09002969B2
公开(公告)日：2015-04-07
申请号：US11632943
申请日：2006-05-18
申请人： Hiroyuki Kimiyama , Tsuyoshi Ogura , Tetsuo Kawano , Kenji Shimizu , Mitsuru Maruyama , Takeshi Kugimoto
发明人： Hiroyuki Kimiyama , Tsuyoshi Ogura , Tetsuo Kawano , Kenji Shimizu , Mitsuru Maruyama , Takeshi Kugimoto
IPC分类号： G06F15/167 , H04N21/231 , H04N21/222 , H04N21/232 , H04N21/845 , H04N21/658
CPC分类号： H04N21/23103 , H04N21/222 , H04N21/232 , H04N21/6581 , H04N21/8456
摘要： A distributed multimedia server system includes a buffer server module, a storage server module, and an intercluster connection network. Based on memory information on a buffer memory of the storage server module that stores divided multimedia information, the buffer server module obtains the divided multimedia information from the buffer memory using remote direct memory access. The storage server module reads the divided multimedia information requested from the buffer server module from a storage device, and stores the divided multimedia information in the buffer memory.
摘要翻译：分布式多媒体服务器系统包括缓冲器服务器模块，存储服务器模块和集群间连接网络。基于存储分割多媒体信息的存储服务器模块的缓冲存储器上的存储器信息，缓冲器服务器模块使用远程直接存储器访问从缓冲存储器获取分割的多媒体信息。存储服务器模块从存储装置读取从缓冲器服务器模块请求的划分的多媒体信息，并将分割的多媒体信息存储在缓冲存储器中。

2. 发明申请

US20080091789A1 Distributed Multi-Media Server System, Multi-Media Information Distribution Method, Program Thereof, and Recording Medium 有权
标题翻译：分布式多媒体服务器系统，多媒体信息分发方法，程序和记录媒体
公开(公告)号：US20080091789A1
公开(公告)日：2008-04-17
申请号：US11632943
申请日：2006-05-18
申请人： Hiroyuki Kimiyama , Tsuyoshi Ogura , Tetsuo Kawano , Kenji Shimizu , Mitsuru Maruyama , Takeshi Kugimoto
发明人： Hiroyuki Kimiyama , Tsuyoshi Ogura , Tetsuo Kawano , Kenji Shimizu , Mitsuru Maruyama , Takeshi Kugimoto
IPC分类号： G06F15/167
CPC分类号： H04N21/23103 , H04N21/222 , H04N21/232 , H04N21/6581 , H04N21/8456
摘要： A distributed multimedia server system includes a buffer server module, a storage server module, and an intercluster connection network. Based on memory information on a buffer memory of the storage server module that stores divided multimedia information, the buffer server module obtains the divided multimedia information from the buffer memory using remote direct memory access. The storage server module reads the divided multimedia information requested from the buffer server module from a storage device, and stores the divided multimedia information in the buffer memory.
摘要翻译：分布式多媒体服务器系统包括缓冲器服务器模块，存储服务器模块和集群间连接网络。基于存储分割多媒体信息的存储服务器模块的缓冲存储器上的存储器信息，缓冲器服务器模块使用远程直接存储器访问从缓冲存储器获取分割的多媒体信息。存储服务器模块从存储装置读取从缓冲器服务器模块请求的划分的多媒体信息，并将分割的多媒体信息存储在缓冲存储器中。

3. 发明申请

US20090164773A1 DYNAMIC RECONFIGURATION SUPPORTING METHOD, DYNAMIC RECONFIGURATION SUPPORTING APPARATUS, AND DYNAMIC RECONFIGURATION SYSTEM 有权
标题翻译：动态重构支持方法，动态重构支持设备和动态重构系统
公开(公告)号：US20090164773A1
公开(公告)日：2009-06-25
申请号：US12332792
申请日：2008-12-11
申请人： Koji ISHIHARA , Tetsuo Kawano , Kyoji Sato , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Masato Kondo
发明人： Koji ISHIHARA , Tetsuo Kawano , Kyoji Sato , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Masato Kondo
IPC分类号： G06F9/00
CPC分类号： G06F15/7871
摘要： A dynamic reconfiguration supporting method that generates a driver function to cause a dynamic reconfiguration circuit to execute a program of an application described in a predetermined language, includes acquiring a configuration defining file representing a configuration of a cluster of the dynamic reconfiguration circuit in execution of the process of the application, generating an address map representing an address of a processing element (to be referred to as “PE” hereinafter) in the cluster on the basis of the configuration defining file acquired by the acquiring operation, generating a driver function that associates the function and an address of the PE which executes the function with reference to the address map, when a PE which executes a function described in the application is allocated from the PE, and creating a driver function file that stores the driver function.
摘要翻译：一种动态重新配置支持方法，其生成驱动器功能以使动态重配置电路执行以预定语言描述的应用的程序，包括获取表示动态重配置电路的集群的配置的配置定义文件，以执行基于通过获取操作获取的配置定义文件，生成表示处理元件（以下称为“PE”）的地址的地址映射，生成将该关联的驱动器功能当从PE分配执行应用程序中描述的功能的PE并创建存储驱动程序功能的驱动程序功能文件时，参考地址映射执行功能的PE的功能和地址。

4. 发明申请

US20090130344A1 COMPOSITION, FILM AND LIQUID CRYSTAL DISPLAY 审中-公开
标题翻译：组合物，电影和液晶显示
公开(公告)号：US20090130344A1
公开(公告)日：2009-05-21
申请号：US12093170
申请日：2006-11-10
申请人： Masaki Okazaki , Takayasu Yasuda , Naoyuki Nishikawa , Tetsuo Kawano
发明人： Masaki Okazaki , Takayasu Yasuda , Naoyuki Nishikawa , Tetsuo Kawano
IPC分类号： G02F1/1335 , C09K19/00 , C09K19/06
CPC分类号： C08J5/18 , C08J2301/10 , C08K5/0008 , C08K9/04 , C08L1/10 , C08L1/12 , C08L1/14 , C08L45/00 , G02B5/3083 , G02F1/133528 , G02F1/13363 , Y10T428/1041
摘要： A novel composition is disclosed. The composition comprises, at least, a polymer material and inorganic fine particles having adsorbed thereto molecules having at least one adsorptive group to the inorganic fine particle and a group capable of forming a liquid crystal core. A film made of the composition is also disclosed.
摘要翻译：公开了一种新型组合物。该组合物至少包含吸附到无机细颗粒上的具有至少一个吸附基团的分子的聚合物材料和无机细颗粒以及能够形成液晶核心的基团。还公开了由该组合物制成的薄膜。

5. 发明申请

US20070230336A1 Reconfigurable circuit 有权
标题翻译：可重构电路
公开(公告)号：US20070230336A1
公开(公告)日：2007-10-04
申请号：US11545477
申请日：2006-10-11
申请人： Takashi Hanai , Tetsuo Kawano
发明人： Takashi Hanai , Tetsuo Kawano
IPC分类号： H04L12/26
CPC分类号： G06F15/7867
摘要： A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.
摘要翻译：可重构电路包括：网络电路，用于控制运算单元组的输出端和输入端之间的连接;以及连接在算术单元组和网络电路之间的第一选择器。当第一控制信号处于第一状态时，第一选择器将运算单元组的第一端连接到网络电路的第一端，并且将运算单元组的第二端连接到网络的第二终端电路。同时，当第一控制信号处于第二状态时，第一选择器将运算单元组的第一端连接到网络电路的第二端，并且将运算单元组的第二端连接到网络电路。

6. 发明授权

US07219320B2 Semiconductor integrated circuit timing analysis apparatus timing analysis method and timing analysis program 失效
标题翻译：半导体集成电路定时分析装置定时分析方法和时序分析程序
公开(公告)号：US07219320B2
公开(公告)日：2007-05-15
申请号：US10807286
申请日：2004-03-24
申请人： Tetsuo Kawano , Satoru Yoshikawa , Toshikatsu Hosono , Shigenori Ichinose , Takashi Yoneda
发明人： Tetsuo Kawano , Satoru Yoshikawa , Toshikatsu Hosono , Shigenori Ichinose , Takashi Yoneda
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.
摘要翻译：根据栅极级的数量，在系数运算单元中计算作为分析对象的路径中的OCV系数，通过根据目标路径中的门级的数量消除每个门的延迟的变化，以及定时分析通过使用考虑了门级数的OCV系数在定时分析单元中执行目标路径的变化，从而根据目标路径中的门级数减少整个路径的变化程度，从而使考虑到半导体集成电路的芯片的变化，可以进行准确的时序分析。

7. 发明授权

US4692783A Gate array 失效
标题翻译：门阵列
公开(公告)号：US4692783A
公开(公告)日：1987-09-08
申请号：US922787
申请日：1986-10-23
申请人： Hideo Monma , Masato Ishiguro , Tetsuo Kawano
发明人： Hideo Monma , Masato Ishiguro , Tetsuo Kawano
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L27/118 , H01L29/78
CPC分类号： H01L27/11807 , H01L21/82
摘要： A gate array is disclosed having a plurality of basic cells each comprising a transistor whose gm is as low as one fifth to one twentieth that of the transistors in a conventional gate array. The low gm is provided by reducing the W/L ratio of the gate region of the transistor. The basic cell having the transistor of the low gm is formed to replace the conventional basic cell at a specified position in a specified basic cell array. The transistor of low gm reduces the number of basic cells necessary for forming a delay circuit, and elminates the need for an external resistance component which was formerly required when a pull-up or pull-down circuit or a monostable multivibrator was formed in the gate array.
摘要翻译：公开了具有多个基本单元的门阵列，每个基本单元包括其常规门阵列中的晶体管的gm低至五分之一至二十分之一的晶体管。通过降低晶体管的栅极区域的W / L比来提供低gm。具有低gm的晶体管的基本单元被形成为在指定的基本单元阵列中的指定位置处替换传统的基本单元。低gm的晶体管减少形成延迟电路所需的基本电池数量，并且最终需要一种外部电阻元件，这在先前在栅极中形成上拉或下拉电路或单稳态多谐振荡器时是需要的数组。

8. 发明授权

US08451022B2 Integrated circuit and input data controlling method for reconfigurable circuit 有权
标题翻译：用于可重构电路的集成电路和输入数据控制方法
公开(公告)号：US08451022B2
公开(公告)日：2013-05-28
申请号：US11802825
申请日：2007-05-25
申请人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
发明人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.
摘要翻译：根据本发明的集成电路包括可重配置方式包括多个计算单元互连的可重构电路和输入数据控制部分。输入数据控制部分控制输入数据，使得响应于可重构电路的配置将数据输入到可重构电路。

9. 发明授权

US08173475B2 Method of producing photoelectric conversion device having a multilayer structure formed on a substrate 有权
标题翻译：一种制造具有形成在基板上的多层结构的光电转换装置的方法
公开(公告)号：US08173475B2
公开(公告)日：2012-05-08
申请号：US13011584
申请日：2011-01-21
申请人： Tetsuo Kawano , Takashi Koike
发明人： Tetsuo Kawano , Takashi Koike
IPC分类号： H01L21/00
CPC分类号： H01L31/0336 , H01L31/0323 , H01L31/03923 , H01L31/03925 , H01L31/0749 , H01L31/18 , Y02E10/541 , Y02P70/521
摘要： A method of producing a photoelectric conversion device having a multilayer structure formed on a substrate, the multilayer structure including a lower electrode, a photoelectric conversion layer made of a compound semiconductor layer, an n-type buffer layer made of a compound semiconductor layer, and a transparent conductive layer, is disclosed. A reaction solution, which is an aqueous solution containing an n-type dopant element, at least one of ammonia and an ammonium salt, and thiourea, is prepared, the n-type dopant is diffused into the photoelectric conversion layer by immersing the substrate including the photoelectric conversion layer in the reaction solution controlled to a temperature in the range from 20° C. to 45° C.; and the buffer layer is deposited on the photoelectric conversion layer by immersing the substrate including the photoelectric conversion layer subjected to the diffusion step in the reaction solution controlled to a temperature in the range from 70° C. to 95° C.
摘要翻译：一种制造具有形成在基板上的多层结构的光电转换装置的方法，所述多层结构包括下电极，由化合物半导体层制成的光电转换层，由化合物半导体层制成的n型缓冲层，以及公开了一种透明导电层。制备作为含有n型掺杂剂元素，氨和铵盐中的至少一种和硫脲的水溶液的反应溶液，将n型掺杂剂浸渍在光电转换层中，将包含将反应溶液中的光电转换层控制在20℃至45℃的温度范围内。并且通过将包含经过扩散步骤的光电转换层的衬底浸入控制在70℃至95℃的温度的反应溶液中，将缓冲层沉积在光电转换层上。

10. 发明授权

US08099540B2 Reconfigurable circuit 有权
标题翻译：可重构电路
公开(公告)号：US08099540B2
公开(公告)日：2012-01-17
申请号：US11545477
申请日：2006-10-11
申请人： Takashi Hanai , Tetsuo Kawano
发明人： Takashi Hanai , Tetsuo Kawano
IPC分类号： G06F13/00 , G06F15/00 , G06F7/38
CPC分类号： G06F15/7867
摘要： A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.
摘要翻译：可重构电路包括：网络电路，用于控制运算单元组的输出端和输入端之间的连接;以及连接在算术单元组和网络电路之间的第一选择器。当第一控制信号处于第一状态时，第一选择器将运算单元组的第一端连接到网络电路的第一端，并且将运算单元组的第二端连接到网络的第二终端电路。同时，当第一控制信号处于第二状态时，第一选择器将运算单元组的第一端连接到网络电路的第二端，并且将运算单元组的第二端连接到网络电路。

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