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1. 发明授权

US08357343B2 Star-shaped zinc oxide particles and method for producing the same 有权
标题翻译：星形氧化锌颗粒及其制造方法
公开(公告)号：US08357343B2
公开(公告)日：2013-01-22
申请号：US12695740
申请日：2010-01-28
申请人： Tetsuo Kawano
发明人： Tetsuo Kawano
IPC分类号： C01G9/00
CPC分类号： C01G9/02 , B82Y30/00 , C01P2002/72 , C01P2004/03 , C01P2004/04 , C01P2004/16 , C01P2004/45 , Y10T428/2982
摘要： A method for producing star-shaped zinc oxide particles, the method including heating a solution containing tetrahydroxozincate(II) ion [Zn(OH)4]2−, and diluting the solution containing tetrahydroxozincate(II) ion [Zn(OH)4]2− with a solvent in the course of reaction so that the concentration of zinc ion (Zn2+) after the dilution is adjusted to 0.008 M or lower.
摘要翻译：一种生产星形氧化锌颗粒的方法，该方法包括加热含有四氢喔啉（II）离子[Zn（OH）4] 2-的溶液，稀释含有四氢inc ate ate（（（[[[[the [[[] 2-在反应过程中用溶剂使稀释后的锌离子（Zn 2+）的浓度调节至0.008M以下。

2. 发明申请

US20100260693A1 COSMETIC COMPOSITION 审中-公开
标题翻译：化妆品组合物
公开(公告)号：US20100260693A1
公开(公告)日：2010-10-14
申请号：US12756691
申请日：2010-04-08
申请人： Tetsuo Kawano , Hiroyuki Hirai , Kazuhiro Nakamura
发明人： Tetsuo Kawano , Hiroyuki Hirai , Kazuhiro Nakamura
IPC分类号： A61K8/27 , A61Q17/04 , C01G9/02 , B32B5/16 , C07F3/06
CPC分类号： C01G9/02 , A61K8/0245 , A61K8/27 , A61K8/585 , A61K2800/412 , A61K2800/623 , A61Q1/02 , A61Q17/04 , C01P2004/03 , C01P2004/04 , C01P2004/45 , C01P2004/62 , Y10T428/2982
摘要： A cosmetic composition contains star-shaped zinc oxide particles each having a star shape, and containing zinc oxide as a main substance thereof.
摘要翻译：化妆品组合物包含星形氧化锌颗粒，其颗粒为星形，并含有氧化锌作为其主要物质。

3. 发明申请

US20080292527A1 Method for Producing Carbonates 审中-公开
标题翻译：生产碳酸盐的方法
公开(公告)号：US20080292527A1
公开(公告)日：2008-11-27
申请号：US11792528
申请日：2005-12-13
申请人： Tetsuo Kawano , Tatsuya Ishizaka
发明人： Tetsuo Kawano , Tatsuya Ishizaka
IPC分类号： C01B31/24
CPC分类号： C01G9/00 , B82Y30/00 , C01F11/18 , C01G21/14 , C01P2004/54 , C01P2004/61 , C01P2004/62 , C01P2004/64
摘要： The object of the present invention is to provide a method for producing carbonates capable of effectively and easily forming carbonates shaped to have an orientational birefringence and an aspect ratio greater than 1 as well as capable of controlling the particle size. For this end, it is a method of which a metallic ion source containing at least one selected from Sr2+ ions, Ca2+ ions, Ba2+ ions, Zn2+ ions, and Pb2+ with a carbonate source in a solution to thereby produce carbonates shaped to have an aspect ratio greater than 1, and the method include increasing the number of carbonate particles and increasing the volume of carbonate particles.
摘要翻译：本发明的目的是提供一种能够有效且容易地形成碳酸酯以形成具有取向双折射和纵横比大于1并且能够控制粒径的碳酸酯的方法。为此，在溶液中，含有选自Sr 2+离子，Ca 2+离子，Ba 2+离子，Zn 2+离子和Pb 2+的至少一种金属离子源与碳酸酯源形成的方法，由此生成形成为具有方面比例大于1，该方法包括增加碳酸盐颗粒的数量和增加碳酸盐颗粒的体积。

4. 发明申请

US20080241048A1 Carbonates and Method for Producing the Same 审中-公开
标题翻译：碳酸盐及其生产方法
公开(公告)号：US20080241048A1
公开(公告)日：2008-10-02
申请号：US12053682
申请日：2008-03-24
申请人： Tetsuo Kawano
发明人： Tetsuo Kawano
IPC分类号： C01B31/24
CPC分类号： C09C1/027 , C01B32/60 , C01F11/184 , C01F11/187 , C01P2002/72 , C01P2004/04 , C01P2004/10 , C01P2004/54 , C01P2004/61 , C01P2004/62 , C01P2006/60 , C09C1/02 , C09C1/021
摘要： The present invention provides a method for producing carbonates, which includes at least adding an aqueous solution containing a carbonate source into an alcoholic solution containing a metal ion source, wherein an alkaline chemical is added when the carbonate source is reacted with the metal ion source.
摘要翻译：本发明提供一种生产碳酸盐的方法，其包括至少将含有碳酸盐源的水溶液加入到含有金属离子源的醇溶液中，其中当碳酸盐源与金属离子源反应时加入碱性化学物质。

5. 发明授权

US07194610B2 Processor and pipeline reconfiguration control method 失效
标题翻译：处理器和管道重新配置控制方法
公开(公告)号：US07194610B2
公开(公告)日：2007-03-20
申请号：US11063860
申请日：2005-02-23
申请人： Shiro Uriu , Mitsuharu Wakayoshi , Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki
发明人： Shiro Uriu , Mitsuharu Wakayoshi , Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki
IPC分类号： G06F13/00
CPC分类号： G06F15/7867 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3897
摘要： A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
摘要翻译：可重配置处理器从硬件配置信息计算执行流水线处理的配置执行时间，并修复时钟周期，直到处理结束为止。计数器将固定时钟周期与实际经过的时钟数进行比较，当经过的时钟数等于时钟周期时，确定流水线处理已经结束，并且通知配置控制器。

6. 发明授权

US07047504B2 Method and program for designing semiconductor integrated circuits to optimize clock skews on plurality of clock paths 有权
标题翻译：用于设计半导体集成电路以优化多个时钟路径上的时钟偏移的方法和程序
公开(公告)号：US07047504B2
公开(公告)日：2006-05-16
申请号：US10369535
申请日：2003-02-21
申请人： Tetsuo Kawano
发明人： Tetsuo Kawano
IPC分类号： G00F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method for designing semiconductor integrated circuits that efficiently optimizes clock skews in a plurality of clock modes in the case of designing semiconductor integrated circuits having a plurality of clock modes. A plurality of clock paths in each of a plurality of clock modes are detected from layout data for a semiconductor integrated circuit. Delay time in all elements on each of the plurality of clock paths detected is collected. A delay adjustment position is set on each of the plurality of clock paths detected. An optimum delay value at the delay adjustment position on each of the plurality of clock paths is calculated by considering delay time at the set delay adjustment position as a nonnegative variable, by formulating a linear expression for each of the plurality of clock paths by use of this variable and the collected delay time in all of the elements, and by working out the linear expression. Circuit structure based on the layout data is corrected automatically by locating a delay element having appropriate delay time at each delay adjustment position on the basis of the delay value calculated.
摘要翻译：在设计具有多个时钟模式的半导体集成电路的情况下，设计有效地优化多个时钟模式中的时钟偏差的半导体集成电路的设计方法。从半导体集成电路的布局数据检测多个时钟模式中的每一个中的多个时钟路径。收集所检测到的多个时钟路径中的每一个上的所有元素的延迟时间。在检测到的多个时钟路径中的每一个上设置延迟调整位置。通过考虑在设定的延迟调整位置处的延迟时间作为非负变量来计算在多个时钟路径中的每一个上的延迟调整位置处的最佳延迟值，通过使用多个时钟路径中的每一个通过使用该变量和收集的所有元素的延迟时间，并通过求出线性表达式。基于布局数据的电路结构通过基于所计算的延迟值定位在每个延迟调整位置具有适当延迟时间的延迟元件来自动校正。

7. 发明申请

US20060010306A1 Reconfigurable operation apparatus 有权
标题翻译：可重构操作装置
公开(公告)号：US20060010306A1
公开(公告)日：2006-01-12
申请号：US11077561
申请日：2005-03-11
申请人： Miyoshi Saito , Hisanori Fujisawa , Hideki Yoshizawa , Tetsu Tanizawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
发明人： Miyoshi Saito , Hisanori Fujisawa , Hideki Yoshizawa , Tetsu Tanizawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
IPC分类号： G06F15/00
CPC分类号： G06F15/8007
摘要： A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.
摘要翻译：可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

8. 发明申请

US20060004993A1 Processor and pipeline reconfiguration control method 失效
标题翻译：处理器和管道重新配置控制方法
公开(公告)号：US20060004993A1
公开(公告)日：2006-01-05
申请号：US11063860
申请日：2005-02-23
申请人： Shiro Uriu , Mitsuharu Wakayoshi , Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki
发明人： Shiro Uriu , Mitsuharu Wakayoshi , Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki
IPC分类号： G06F9/00
CPC分类号： G06F15/7867 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3897
摘要： A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
摘要翻译：可重构处理器根据硬件配置信息计算执行流水线处理的配置执行时间，并修复时钟周期，直到处理结束为止。计数器将固定时钟周期与实际经过的时钟数进行比较，当经过的时钟数等于时钟周期时，确定流水线处理已经结束，并且通知配置控制器。

9. 发明申请

US20050289327A1 Reconfigurable processor and semiconductor device 审中-公开
标题翻译：可重配置的处理器和半导体器件
公开(公告)号：US20050289327A1
公开(公告)日：2005-12-29
申请号：US11037049
申请日：2005-01-19
申请人： Ichiro Kasama , Toshiaki Suzuki , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa
发明人： Ichiro Kasama , Toshiaki Suzuki , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa
IPC分类号： G06F9/30 , G06F9/46 , G06F15/00
CPC分类号： G06F9/461 , G06F9/3885 , G06F9/3897
摘要： A reconfigurable processor in which an application can be switched more freely. A switching condition associating section associates output from a plurality of arithmetic and logic unit modules used as switching conditions for switching the operation of an arithmetic and logic unit group with a plurality of states indicative of switching condition codes. When a switching condition code output section decides that a switching condition comes into existence on the basis of the output from the plurality of arithmetic and logic unit modules set as the switching conditions, the switching condition code output section outputs a switching condition code corresponding to the switching condition which comes into existence. When a sequencer accepts the switching condition code, the sequencer switches the arithmetic and logic unit group to a state corresponding to the switching condition code.
摘要翻译：可重新配置的处理器，其中可以更自由地切换应用。切换条件关联部分将用作切换条件的多个算术和逻辑单元模块的输出相关联，用于切换算术和逻辑单元组的操作与表示切换条件代码的多个状态。当切换条件代码输出部根据设定为切换条件的多个算术逻辑单元模块的输出决定切换条件成立时，切换条件代码输出部输出对应于切换条件成立。当定序器接受切换条件代码时，定序器将算术和逻辑单元组切换到与切换条件代码相对应的状态。

10. 发明申请

US20050081171A1 Timing analysis apparatus, timing analysis method and program product 失效
标题翻译：定时分析仪器，时序分析方法和程序产品
公开(公告)号：US20050081171A1
公开(公告)日：2005-04-14
申请号：US10807286
申请日：2004-03-24
申请人： Tetsuo Kawano , Satoru Yoshikawa , Toshikatsu Hosono , Shigenori Ichinose , Takashi Yoneda
发明人： Tetsuo Kawano , Satoru Yoshikawa , Toshikatsu Hosono , Shigenori Ichinose , Takashi Yoneda
IPC分类号： G06F17/50 , G06F9/45 , H01L21/82
CPC分类号： G06F17/5031
摘要： OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.
摘要翻译：根据栅极级的数量，在系数运算单元中计算作为分析对象的路径中的OCV系数，通过根据目标路径中的门级的数量消除每个门的延迟的变化，以及定时分析通过使用考虑了门级数的OCV系数在定时分析单元中执行目标路径的变化，从而根据目标路径中的门级数减少整个路径的变化程度，从而使考虑到半导体集成电路的芯片的变化，可以进行准确的时序分析。

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