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1. 发明授权

US10438383B2 Display device 有权
公开(公告)号：US10438383B2
公开(公告)日：2019-10-08
申请号：US15370630
申请日：2016-12-06
申请人： HITACHI, LTD.
发明人： Tadanobu Toba , Takumi Uezono , Yusuke Kanno , Masahiro Shiraishi , Hideo Harada , Satoru Akasaka
IPC分类号： G06T15/00 , G06T11/20 , G06F3/14 , G05B23/02
摘要： The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside. This improves safety and reliability when severe safety criteria are required such as in a case of monitor-display in industrial plant equipment.

2. 发明授权

US10095570B2 Programmable device, error storage system, and electronic system device 有权
公开(公告)号：US10095570B2
公开(公告)日：2018-10-09
申请号：US15110278
申请日：2014-01-24
申请人： Hitachi, Ltd.
发明人： Tadanobu Toba , Kenichi Shimbo , Yusuke Kanno , Nobuyasu Kanekawa , Kotaro Shimamura , Hiromichi Yamada
IPC分类号： G06F11/00 , G06F11/07 , H03K19/177
摘要： The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.

3. 发明授权

US09735784B2 Programmable logic device and logic integration tool 有权
公开(公告)号：US09735784B2
公开(公告)日：2017-08-15
申请号：US15025821
申请日：2013-09-30
申请人： Hitachi, Ltd.
发明人： Yusuke Kanno , Nobuyasu Kanekawa , Kotaro Shimamura , Tadanobu Toba , Teppei Hirotsu , Tsutomu Yamada
IPC分类号： H03K19/177 , H03K19/21 , H03K19/00
CPC分类号： H03K19/17764 , H03K19/17728 , H03K19/1776 , H03K19/21
摘要： An object of the present invention is to provide a high reliable/high safe programmable logic device with high error resistance. The present invention provides a programmable logic device that has a plurality of configuration memories. The configuration memories are divided into a plurality of areas and are arranged and a part of the plurality of areas is set to a high reliable area where reliability of the configuration memory is higher than in the other area.

4. 发明授权

US10339242B2 Semiconductor LSI design device and design method 有权
公开(公告)号：US10339242B2
公开(公告)日：2019-07-02
申请号：US15622805
申请日：2017-06-14
申请人： Hitachi, Ltd.
发明人： Takumi Uezono , Tadanobu Toba , Yusuke Kanno , Masahiro Shiraishi , Hideo Harada , Satoshi Nishikawa , Toru Motoya
IPC分类号： G06F17/50
摘要： Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

5. 发明授权

US10033357B2 Semiconductor device 有权
公开(公告)号：US10033357B2
公开(公告)日：2018-07-24
申请号：US15028568
申请日：2013-10-16
申请人： Hitachi, Ltd.
发明人： Yusuke Kanno , Takeshi Sakata , Nobuyasu Kanekawa
IPC分类号： H03K3/037 , H03K19/23 , H03K3/3562 , H03K19/0948 , H03K19/177 , H03K19/20
摘要： Provided is a semiconductor device capable of reducing a penalty associated with ensuring reliability. The semiconductor device includes a latch circuit which has input/output paths of three systems or more independent from each other. The latch circuit includes a plurality of storage elements STE1 to STE3 which are provided on the input/output paths of the three systems or more, respectively, and hold input data in synchronization with a clock signal. At least one storage element (for example, STE1) of the plurality of storage elements STE1 to STE3 includes a majority decision unit (for example, 81a) executing a majority decision using data from the storage elements provided on other input/output paths different from the input/output path thereof and outputs data in which a result of the majority decision is reflected.

6. 发明授权

US09337838B2 Programmable circuit device and configuration information restoration method 有权
标题翻译：可编程电路器件及配置信息恢复方法
公开(公告)号：US09337838B2
公开(公告)日：2016-05-10
申请号：US14593029
申请日：2015-01-09
申请人： Hitachi, Ltd.
发明人： Makoto Saen , Takeshi Sakata , Masashi Ohkawa , Yusuke Kanno
IPC分类号： G06F11/07 , H03K19/007 , H03K19/177 , G06F11/18
CPC分类号： H03K19/0075 , G06F11/183 , G06F11/185 , H03K19/17764
摘要： In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.
摘要翻译：在包括可编程电路的装置中，可编程电路连接到其中存储配置信息的非易失性存储器以及具有比非易失性存储器更快的读取速度的另一个存储器，并且可编程电路包括配置存储器控制电路和信号线组，用于通过配置存储器控制电路对来自非易失性存储器的诸如易失性存储器和嵌入式存储器的其他存储器进行读取，并且将一部分电路配置信息复制到将其从故障中迅速恢复到其他内存中。

7. 发明授权

US08976608B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08976608B2
公开(公告)日：2015-03-10
申请号：US13910507
申请日：2013-06-05
申请人： Hitachi, Ltd.
发明人： Goichi Ono , Yusuke Kanno , Akira Kotabe
IPC分类号： G11C7/00 , G11C8/08 , G11C29/50 , G11C11/41 , G11C29/12
CPC分类号： G11C7/00 , G11C8/08 , G11C11/41 , G11C29/50 , G11C2029/1202
摘要： A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.
摘要翻译：提供了一种半导体集成电路器件，其检测由随时间变化的器件变化引起的SRAM的操作误差。在SRAM中，存储单元具有栅极连接到字线的转移MOS晶体管。在存储单元的写入测试时，包括测试/正常操作选择电路和字线驱动电路的控制电路在写入测试数据之前的准备周期中向字线施加第三电压，此后，第一电压到字线，以及在写入结束时到字线的第二电压。由此，可以控制随时间变动的转移MOS晶体管的阈值电压。因此，可以提高由于时间变化导致的SRAM的故障单元的检测效率。

8. 发明申请

US20130322188A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20130322188A1
公开(公告)日：2013-12-05
申请号：US13910507
申请日：2013-06-05
申请人： Hitachi, Ltd.
发明人： Goichi Ono , Yusuke Kanno , Akira Kotabe
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C8/08 , G11C11/41 , G11C29/50 , G11C2029/1202
摘要： A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.
摘要翻译：提供了一种半导体集成电路器件，其检测由随时间变化的器件变化引起的SRAM的操作误差。在SRAM中，存储单元具有栅极连接到字线的转移MOS晶体管。在存储单元的写入测试时，包括测试/正常操作选择电路和字线驱动电路的控制电路在写入测试数据之前的准备周期中向字线施加第三电压，此后，第一电压到字线，以及在写入结束时到字线的第二电压。由此，可以控制随时间变动的转移MOS晶体管的阈值电压。因此，可以提高由于时间变化导致的SRAM的故障单元的检测效率。

9. 发明申请

US20210326738A1 SILICON ELECTRON SPIN TYPE MASSIVELY PARALLEL QUANTUM COMPUTER 有权
公开(公告)号：US20210326738A1
公开(公告)日：2021-10-21
申请号：US17206326
申请日：2021-03-19
申请人： Hitachi, Ltd.
发明人： Yusuke Kanno , Hiroyuki Mizuno , Ryuta Tsuchiya , Noriyuki Lee , Gou Shinkai , Tatsuya Tomaru
IPC分类号： G06N10/00 , G06F9/38 , G06F17/18
摘要： A quantum computer includes: a module including quantum computation units having a plurality of qubits and selection units that cause the quantum computation units to perform parallel computations; and a read unit that acquires computation results of the quantum computation units of a plurality of modules and performs statistical averaging on the plurality of acquired computation results.

10. 发明授权

US10929273B2 Application logic, and verification method and configuration method thereof 有权
公开(公告)号：US10929273B2
公开(公告)日：2021-02-23
申请号：US15621519
申请日：2017-06-13
申请人： HITACHI, LTD.
发明人： Toru Motoya , Masahiro Shiraishi , Satoshi Nishikawa , Keisuke Yamamoto , Tadanobu Toba , Takumi Uezono , Hideo Harada , Yusuke Kanno
IPC分类号： G06F11/36 , G21C17/00 , G21D3/00 , G06F30/3323 , G06F9/30
摘要： A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

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