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1. 发明申请

US20130095637A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20130095637A1
公开(公告)日：2013-04-18
申请号：US13586325
申请日：2012-08-15
申请人： Honggun KIM , Seung-Heon Lee , Mansug Kang , ByeongJu Bae , Eunkee Hong
发明人： Honggun KIM , Seung-Heon Lee , Mansug Kang , ByeongJu Bae , Eunkee Hong
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of fabricating a semiconductor device, the method including forming a mask layer on a semiconductor substrate; forming a trench in the semiconductor substrate using the mask layer as an etch mask; forming a first layer in the trench; and performing a first thermal treatment process on the first layer such that the first thermal treatment process is performed under an atmosphere that includes ozone and water vapor and transforms the first layer into a second layer.
摘要翻译：一种制造半导体器件的方法，所述方法包括在半导体衬底上形成掩模层; 在所述半导体衬底中使用所述掩模层作为蚀刻掩模形成沟槽; 在沟槽中形成第一层; 以及在所述第一层上进行第一热处理工艺，使得所述第一热处理工艺在包括臭氧和水蒸气的气氛下进行，并将所述第一层转化为第二层。

2. 发明申请

US20130052780A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130052780A1
公开(公告)日：2013-02-28
申请号：US13546518
申请日：2012-07-11
申请人： Honggun Kim , ByeongJu Bae , Seung-Heon Lee , Mansug Kang , Eunkee Hong
发明人： Honggun Kim , ByeongJu Bae , Seung-Heon Lee , Mansug Kang , Eunkee Hong
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/02164 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894
摘要： In a method of fabricating a semiconductor device, isolation structures are formed in a substrate to define active regions. Conductive structures are formed on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction. An interfacial layer is conformally formed on the substrate in contact with the conductive structures. A first insulation layer is provided on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed.
摘要翻译：在制造半导体器件的方法中，隔离结构形成在衬底中以限定有源区。导电结构形成在衬底上以交叉至少两个有源区和隔离结构，导电结构沿第一方向延伸。在与导电结构接触的衬底上共形形成界面层。第一绝缘层设置在界面层上，其中使用可流动化学气相沉积（CVD）工艺形成第一绝缘层，并且其中界面层减小在导电结构和第一绝缘体之间的界面处产生的拉伸应力同时形成第一绝缘层。

3. 发明授权

US08748263B2 Methods of fabricating a semiconductor device comprising a conformal interfacial layer 有权
标题翻译：制造包括保形界面层的半导体器件的方法
公开(公告)号：US08748263B2
公开(公告)日：2014-06-10
申请号：US13546518
申请日：2012-07-11
申请人： Honggun Kim , ByeongJu Bae , Seung-Heon Lee , Mansug Kang , Eunkee Hong
发明人： Honggun Kim , ByeongJu Bae , Seung-Heon Lee , Mansug Kang , Eunkee Hong
IPC分类号： H01L21/8242 , H01L21/768 , H01L21/02
CPC分类号： H01L21/76897 , H01L21/02164 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894
摘要： In a method of fabricating a semiconductor device, isolation structures are formed in a substrate to define active regions. Conductive structures are formed on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction. An interfacial layer is conformally formed on the substrate in contact with the conductive structures. A first insulation layer is provided on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed.
摘要翻译：在制造半导体器件的方法中，隔离结构形成在衬底中以限定有源区。导电结构形成在衬底上以交叉至少两个有源区和隔离结构，导电结构沿第一方向延伸。在与导电结构接触的衬底上共形形成界面层。第一绝缘层设置在界面层上，其中使用可流动化学气相沉积（CVD）工艺形成第一绝缘层，并且其中界面层减小在导电结构和第一绝缘体之间的界面处产生的拉伸应力同时形成第一绝缘层。

4. 发明授权

US08835315B2 Methods of fabricating semiconductor memory devices including support patterns 有权
标题翻译：制造包括支持图案的半导体存储器件的方法
公开(公告)号：US08835315B2
公开(公告)日：2014-09-16
申请号：US13371127
申请日：2012-02-10
申请人： Kyungmun Byun , Hyongsoo Kim , Eunkee Hong , Mansug Kang
发明人： Kyungmun Byun , Hyongsoo Kim , Eunkee Hong , Mansug Kang
IPC分类号： H01L27/108 , H01L49/02
CPC分类号： H01L27/10808 , H01L27/10852 , H01L28/90
摘要： A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern.
摘要翻译：电容器电介质可以在存储节点和电极层之间。支撑图案可以连接到存储节点，其中支撑图案可以包括至少一个第一图案和彼此分层的至少一个第二图案，其中第一图案可以包括具有相对于第二图案的蚀刻选择性的材料模式。

5. 发明授权

US08927389B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08927389B2
公开(公告)日：2015-01-06
申请号：US13369476
申请日：2012-02-09
申请人： Kyungmun Byun , Byoungdeog Choi , Eunkee Hong , Mansug Kang
发明人： Kyungmun Byun , Byoungdeog Choi , Eunkee Hong , Mansug Kang
IPC分类号： H01L21/00 , H01L27/105 , H01L27/108 , H01L29/94 , H01L21/762 , H01L27/115
CPC分类号： H01L21/76229 , H01L27/1052 , H01L27/10894 , H01L27/11531 , H01L29/945
摘要： A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region, forming a first trench having a first width in the first region and a second trench having a second width in the second region, and the second width is greater than the first width. The method also includes forming a first insulation layer in the first and second trenches, removing the first insulation layer in the second trench to form a first insulation pattern that includes the first insulation layer remaining in the first trench, forming on the substrate a second insulation layer that fills the second trench, and the second insulation layer includes a different material from the first insulation layer.
摘要翻译：一种制造半导体器件的方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成具有第一宽度的第一沟槽和在第二区域中具有第二宽度的第二沟槽，第二宽度为大于第一宽度。该方法还包括在第一沟槽和第二沟槽中形成第一绝缘层，去除第二沟槽中的第一绝缘层以形成第一绝缘图案，其包括残留在第一沟槽中的第一绝缘层，在衬底上形成第二绝缘层层，其填充第二沟槽，并且第二绝缘层包括与第一绝缘层不同的材料。

6. 发明申请

US20120217560A1 Semiconductor Memory Devices Including Support Patterns 有权
标题翻译：包括支持模式的半导体存储器件
公开(公告)号：US20120217560A1
公开(公告)日：2012-08-30
申请号：US13371127
申请日：2012-02-10
申请人： Kyungmun Byun , Hyongsoo Kim , Eunkee Hong , Mansug Kang
发明人： Kyungmun Byun , Hyongsoo Kim , Eunkee Hong , Mansug Kang
IPC分类号： H01L27/108
CPC分类号： H01L27/10808 , H01L27/10852 , H01L28/90
摘要： A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern.
摘要翻译：电容器电介质可以在存储节点和电极层之间。支撑图案可以连接到存储节点，其中支撑图案可以包括至少一个第一图案和彼此分层的至少一个第二图案，其中第一图案可以包括具有相对于第二图案的蚀刻选择性的材料模式。

7. 发明申请

US20120252182A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120252182A1
公开(公告)日：2012-10-04
申请号：US13369476
申请日：2012-02-09
申请人： Kyungmun BYUN , Byoungdeog Choi , Eunkee Hong , Mansug Kang
发明人： Kyungmun BYUN , Byoungdeog Choi , Eunkee Hong , Mansug Kang
IPC分类号： H01L21/8239
CPC分类号： H01L21/76229 , H01L27/1052 , H01L27/10894 , H01L27/11531 , H01L29/945
摘要： A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region, forming a first trench having a first width in the first region and a second trench having a second width in the second region, and the second width is greater than the first width. The method also includes forming a first insulation layer in the first and second trenches, removing the first insulation layer in the second trench to form a first insulation pattern that includes the first insulation layer remaining in the first trench, forming on the substrate a second insulation layer that fills the second trench, and the second insulation layer includes a different material from the first insulation layer.
摘要翻译：一种制造半导体器件的方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成具有第一宽度的第一沟槽和在第二区域中具有第二宽度的第二沟槽，第二宽度为大于第一宽度。该方法还包括在第一沟槽和第二沟槽中形成第一绝缘层，去除第二沟槽中的第一绝缘层以形成第一绝缘图案，其包括残留在第一沟槽中的第一绝缘层，在衬底上形成第二绝缘层层，其填充第二沟槽，并且第二绝缘层包括与第一绝缘层不同的材料。

8. 发明授权

US08476715B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08476715B2
公开(公告)日：2013-07-02
申请号：US12956578
申请日：2010-11-30
申请人： Honggun Kim , YongSoon Choi , Ha-Young Yi , Eunkee Hong
发明人： Honggun Kim , YongSoon Choi , Ha-Young Yi , Eunkee Hong
IPC分类号： H01L21/70 , H01L21/8234
CPC分类号： H01L29/792 , H01L27/11568 , H01L27/11578
摘要： A semiconductor device and a method of fabricating thereof, including preparing a substrate including a first and second region; forming first and second conductive lines on the first and second region, respectively, the first conductive lines being spaced apart at a first interval and the second conductive lines being spaced apart at a second interval wider than the first interval; forming a dielectric layer in spaces between the first and second conductive lines; etching the dielectric layer until a top surface thereof is lower than top surfaces of the first conductive lines and the second conductive lines; forming a spacer on the etched dielectric layer such that the spacer covers an entire top surface of the etched dielectric layer between the first conductive lines and exposes portions of the etched dielectric layer between the second conductive lines; and removing portions of the etched dielectric layer between the second conductive lines.
摘要翻译：一种半导体器件及其制造方法，包括制备包括第一和第二区域的衬底; 在第一和第二区域分别形成第一和第二导线，第一导线以第一间隔间隔开，第二导线以比第一间隔更宽的第二间隔隔开; 在第一和第二导电线之间的空间中形成电介质层; 蚀刻介电层，直到其顶表面低于第一导电线和第二导线的顶表面; 在所述蚀刻的电介质层上形成间隔物，使得所述间隔物覆盖所述第一导电线之间的所述蚀刻的电介质层的整个顶表面，并且在所述第二导电线之间暴露所述蚀刻的电介质层的部分; 以及去除所述第二导电线之间的蚀刻介电层的部分。

9. 发明授权

US08455985B2 Integrated circuit devices having selectively strengthened composite interlayer insulation layers and methods of fabricating the same 有权
标题翻译：具有选择性强化复合层间绝缘层的集成电路器件及其制造方法
公开(公告)号：US08455985B2
公开(公告)日：2013-06-04
申请号：US13019520
申请日：2011-02-02
申请人： Kyu-hee Han , Sang-hoon Ahn , Eunkee Hong
发明人： Kyu-hee Han , Sang-hoon Ahn , Eunkee Hong
IPC分类号： H01L29/00
CPC分类号： H01L23/562 , H01L21/02126 , H01L21/02274 , H01L21/76801 , H01L21/76825 , H01L23/5258 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L24/04 , H01L24/05 , H01L24/16 , H01L24/48 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/48137 , H01L2224/48145 , H01L2224/48245 , H01L2224/48247 , H01L2224/48463 , H01L2224/85205 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/14 , H01L2224/05552 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.
摘要翻译：集成电路器件包括多个堆叠电路层，所述多个电路层中的至少一个包括复合层间绝缘层，所述复合层间绝缘层包括具有不同机械强度和介电特性的横向相邻的第一和第二绝缘材料区域，以及设置的多个电路部件在复合层间绝缘层中。第一绝缘材料区域可以具有比第二绝缘材料区域更低的介电常数和更低的机械强度，使得例如第一绝缘材料区域可以位于信号线附近或其他电路特征处以在使用第二绝缘材料区域时降低电容绝缘材料区域靠近容易受到局部机械应力的位置，诸如熔断器位置，外部连接接合位置或划线位置。

10. 发明授权

US08367535B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08367535B2
公开(公告)日：2013-02-05
申请号：US13053668
申请日：2011-03-22
申请人： Yong-Soon Choi , Ha-Young Yi , Gil-Heyun Choi , Eunkee Hong , Sang-Hoon Ahn
发明人： Yong-Soon Choi , Ha-Young Yi , Gil-Heyun Choi , Eunkee Hong , Sang-Hoon Ahn
IPC分类号： H01L21/28
CPC分类号： H01L21/28052 , H01L21/28273 , H01L21/76834 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.
摘要翻译：本文的示例性实施例涉及制造半导体器件的方法。该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

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