专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08665629B2 Condensed memory cell structure using a FinFET 有权
标题翻译：使用FinFET的冷凝存储单元结构
公开(公告)号：US08665629B2
公开(公告)日：2014-03-04
申请号：US11864575
申请日：2007-09-28
申请人： Human Park , Ulrich Klostermann , Rainer Leuschner
发明人： Human Park , Ulrich Klostermann , Rainer Leuschner
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , H01L27/2436 , H01L29/66795 , H01L29/785
摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.
摘要翻译：对集成电路的集成电路及其制造方法进行说明。在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于翅片结构的高度。

2. 发明申请

US20090085121A1 Condensed Memory Cell Structure Using a FinFET 有权
标题翻译：使用FinFET的冷凝记忆单元结构
公开(公告)号：US20090085121A1
公开(公告)日：2009-04-02
申请号：US11864575
申请日：2007-09-28
申请人： Human Park , Ulrich Klostermann , Rainer Leuschner
发明人： Human Park , Ulrich Klostermann , Rainer Leuschner
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/228 , H01L27/2436 , H01L29/66795 , H01L29/785
摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.
摘要翻译：对集成电路的集成电路及其制造方法进行说明。在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于翅片结构的高度。

3. 发明申请

US20070069296A1 High-density high current device cell 审中-公开
标题翻译：高密度大电流器件电池
公开(公告)号：US20070069296A1
公开(公告)日：2007-03-29
申请号：US11369194
申请日：2006-03-06
申请人： Human Park , Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
发明人： Human Park , Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
IPC分类号： H01L27/12
CPC分类号： H01L27/228 , B82Y10/00
摘要： A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size to be decreased without decreasing the current that is driven by the transistor. According to the invention, this is achieved by increasing the length of gate portions of one or more transistors within the active area of a cell to increase the effective transistor width. In one embodiment, two transistors, electrically connected in parallel, are used per cell. The two transistors double the effective transistor width within the cell relative to a single transistor design. Such cell designs can be used with a variety of devices, including various types of MRAM and PCRAM.
摘要翻译：描述了通过将电池中的晶体管的有效宽度增加到大于电池的有效面积的实际宽度来减小大电流器件（例如MRAM）中的电池单元尺寸的电池设计和方法。这允许在不降低由晶体管驱动的电流的情况下降低电池尺寸。根据本发明，这通过增加单元的有效区域内的一个或多个晶体管的栅极部分的长度来增加有效晶体管宽度来实现。在一个实施例中，每个单元使用并联电连接的两个晶体管。两个晶体管相对于单晶体管设计，使单元内的有效晶体管宽度倍增。这样的单元设计可以与各种设备一起使用，包括各种类型的MRAM和PCRAM。

4. 发明授权

US07855435B2 Integrated circuit, method of manufacturing an integrated circuit, and memory module 有权
标题翻译：集成电路，集成电路的制造方法和存储器模块
公开(公告)号：US07855435B2
公开(公告)日：2010-12-21
申请号：US12047167
申请日：2008-03-12
申请人： Ulrich Klostermann , Rainer Leuschner
发明人： Ulrich Klostermann , Rainer Leuschner
IPC分类号： H01L23/48
CPC分类号： H01L43/08 , G11C11/15 , G11C11/1675
摘要： According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.
摘要翻译：根据本发明的一个实施例，提供了包括多个存储单元的集成电路。每个存储单元包括电阻率变化存储元件，其包括设置在顶部电极和底部电极之间的顶部电极，底部电极和电阻率变化材料。每个电阻率变化记忆元件至少部分地被绝热结构包围。热绝缘结构被布置成使得在电阻率变化的存储元件内产生的热量消耗到电阻率变化存储元件的环境中降低。

5. 发明授权

US07697322B2 Integrated circuits; method for manufacturing an integrated circuit; method for decreasing the influence of magnetic fields; memory module 失效
标题翻译：集成电路; 集成电路制造方法; 降低磁场影响的方法; 内存模块
公开(公告)号：US07697322B2
公开(公告)日：2010-04-13
申请号：US11775599
申请日：2007-07-10
申请人： Rainer Leuschner , Ulrich Klostermann
发明人： Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/15 , H01L27/222 , H01L43/08
摘要： Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction may include a free layer with a magnetization orientation that is selected by the application of a write current through the magnetic tunnel junction, and a retention layer that retains the selectable magnetization orientation of the free layer at temperatures below a retention temperature.
摘要翻译：本发明的实施例一般涉及集成电路，集成电路的制造方法，减小磁场影响的方法以及存储器模块。在本发明的实施例中，提供了具有磁性隧道结的集成电路。磁性隧道结可以包括具有通过施加通过磁性隧道结的写入电流而选择的磁化取向的自由层，以及在低于保持温度的温度下保持自由层的可选磁化取向的保留层。

6. 发明申请

US20090273966A1 Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit 有权
标题翻译：集成电路，存储单元阵列，存储器模块和操作集成电路的方法
公开(公告)号：US20090273966A1
公开(公告)日：2009-11-05
申请号：US12114466
申请日：2008-05-02
申请人： Dietmar Gogl , Rainer Leuschner , Ulrich Klostermann
发明人： Dietmar Gogl , Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/02
CPC分类号： G11C11/1675 , G11C11/1659
摘要： According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.
摘要翻译：根据本发明的一个实施例，集成电路包括多个热可选择存储单元，每个存储单元连接到导电线，该导线具有用于施加加热电流的第一部分和用于施加加热电流的第二部分编程电流。集成电路被配置为使得加热电流和编程电流可以彼此独立地分别路由到导线的第一和第二部分。

7. 发明申请

US20090016096A1 Integrated Circuits; Method for Manufacturing an Integrated Circuit; Method for Decreasing the Influence of Magnetic Fields; Memory Module 失效
标题翻译：集成电路; 集成电路制造方法降低磁场影响的方法内存模块
公开(公告)号：US20090016096A1
公开(公告)日：2009-01-15
申请号：US11775599
申请日：2007-07-10
申请人： Rainer Leuschner , Ulrich Klostermann
发明人： Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/00 , H01L21/00
CPC分类号： G11C11/15 , H01L27/222 , H01L43/08
摘要： Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction may include a free layer with a magnetization orientation that is selected by the application of a write current through the magnetic tunnel junction, and a retention layer that retains the selectable magnetization orientation of the free layer at temperatures below a retention temperature.
摘要翻译：本发明的实施例一般涉及集成电路，集成电路的制造方法，减小磁场影响的方法以及存储器模块。在本发明的实施例中，提供了具有磁性隧道结的集成电路。磁性隧道结可以包括具有通过施加通过磁性隧道结的写入电流而选择的磁化取向的自由层，以及在低于保持温度的温度下保持自由层的可选磁化取向的保留层。

8. 发明授权

US07092284B2 MRAM with magnetic via for storage of information and field sensor 失效
公开(公告)号：US07092284B2
公开(公告)日：2006-08-15
申请号：US10922434
申请日：2004-08-20
申请人： Daniel Braun , Rainer Leuschner , Ulrich Klostermann
发明人： Daniel Braun , Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/14
CPC分类号： G11C11/15
摘要： A magnetic memory element is disclosed. The magnetic memory element includes a magnetic via for storing information, made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic via having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the magnetic via, wherein the magnetic sensor element being conductively connected to said at least one current line.

9. 发明申请

US20090230379A1 Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module 有权
标题翻译：集成电路，制造集成电路的方法和存储器模块
公开(公告)号：US20090230379A1
公开(公告)日：2009-09-17
申请号：US12047167
申请日：2008-03-12
申请人： Ulrich Klostermann , Rainer Leuschner
发明人： Ulrich Klostermann , Rainer Leuschner
IPC分类号： H01L45/00 , H01L21/762
CPC分类号： H01L43/08 , G11C11/15 , G11C11/1675
摘要： According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.
摘要翻译：根据本发明的一个实施例，提供了包括多个存储单元的集成电路。每个存储单元包括电阻率变化存储元件，其包括设置在顶部电极和底部电极之间的顶部电极，底部电极和电阻率变化材料。每个电阻率变化记忆元件至少部分地被绝热结构包围。热绝缘结构被布置成使得在电阻率变化的存储元件内产生的热量消耗到电阻率变化存储元件的环境中降低。

10. 发明授权

US07075807B2 Magnetic memory with static magnetic offset field 失效
标题翻译：具有静磁场的磁记忆体
公开(公告)号：US07075807B2
公开(公告)日：2006-07-11
申请号：US10920562
申请日：2004-08-18
申请人： Rainer Leuschner , Daniel Braun , Gill Yong Lee , Ulrich Klostermann
发明人： Rainer Leuschner , Daniel Braun , Gill Yong Lee , Ulrich Klostermann
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/16 , H01L43/08
摘要： A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.
摘要翻译：磁阻或磁存储元件和具有一个或多个磁存储元件的磁随机存取存储器。存储元件包括包含第一和第二磁性层的磁性隧道结。第一磁性层具有自由磁化。第一磁性层的自由磁化磁耦合到第一电流线和用于切换自由磁化的第二电流线，以及用于在第一和第二电流中的至少一个方向上施加静态磁偏移场的机构线条。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式