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1. 发明授权

US07979758B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07979758B2
公开(公告)日：2011-07-12
申请号：US12154870
申请日：2008-05-28
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译：半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷在晶圆级别。

2. 发明授权

US07835219B2 Multi-port memory device 有权
标题翻译：多端口存储设备
公开(公告)号：US07835219B2
公开(公告)日：2010-11-16
申请号：US11647617
申请日：2006-12-28
申请人： Hwang Hur , Jae-Il Kim
发明人： Hwang Hur , Jae-Il Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/10 , G11C7/1048 , G11C7/1075
摘要： A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal.
摘要翻译：一种包括多个端口，多个存储体和多个存储体控制器的多端口存储器件，其中所有存储体控制器共享所有端口，该器件包括用于产生内部的锁相环（PLL）单元时钟信号; 延迟单元，设置在每个存储体控制器中，用于通过延迟内部时钟信号产生第一和第二延迟的时钟信号; 设置在每个存储体控制器中的串行器，用于响应于第一延迟时钟信号从所有端口接收多个并行数据并针对对应的数据帧拟合并行数据; 以及设置在每个存储体控制器中的命令解码器，用于解码串行器的输出数据，以响应于第二延迟的时钟信号产生命令信号。

3. 发明授权

US07808851B2 Test circuit for multi-port memory device 有权
标题翻译：多端口存储器件测试电路
公开(公告)号：US07808851B2
公开(公告)日：2010-10-05
申请号：US12474243
申请日：2009-05-28
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
IPC分类号： G11C29/00
CPC分类号： G11C29/26 , G11C8/16 , G11C11/401
摘要： A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode.
摘要翻译：半导体存储器件包括用于传送读取数据的读出总线; 用于传送写入数据的写入总线; 以及临时数据存储单元，连接在读总线和写总线之间，并由在测试模式期间启用的测试模式信号控制。

4. 发明申请

US20080077747A1 Multi-port memory device 有权
标题翻译：多端口存储设备
公开(公告)号：US20080077747A1
公开(公告)日：2008-03-27
申请号：US11647617
申请日：2006-12-28
申请人： Hwang Hur , Jae-Il Kim
发明人： Hwang Hur , Jae-Il Kim
IPC分类号： G06F13/00
CPC分类号： G11C7/10 , G11C7/1048 , G11C7/1075
摘要： A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal.
摘要翻译：一种包括多个端口，多个存储体和多个存储体控制器的多端口存储器件，其中所有存储体控制器共享所有端口，该器件包括用于产生内部的锁相环（PLL）单元时钟信号; 延迟单元，设置在每个存储体控制器中，用于通过延迟内部时钟信号产生第一和第二延迟的时钟信号; 设置在每个存储体控制器中的串行器，用于响应于第一延迟时钟信号从所有端口接收多个并行数据并针对对应的数据帧拟合并行数据; 以及设置在每个存储体控制器中的命令解码器，用于解码串行器的输出数据，以响应于第二延迟的时钟信号产生命令信号。

5. 发明授权

US08225150B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08225150B2
公开(公告)日：2012-07-17
申请号：US13149683
申请日：2011-05-31
申请人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
发明人： Hwang Hur , Chang-Ho Do , Jae-Bum Ko , Jin-Il Chung
IPC分类号： G11C29/00 , G01R31/28 , H03M13/00
CPC分类号： G11C29/12 , G11C11/401
摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.
摘要翻译：半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷在晶圆级别。

6. 发明授权

US08054702B2 Semiconductor memory device with signal aligning circuit 有权
标题翻译：具有信号对准电路的半导体存储器件
公开(公告)号：US08054702B2
公开(公告)日：2011-11-08
申请号：US12472252
申请日：2009-05-26
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
IPC分类号： G11C7/00
CPC分类号： G11C29/34 , G11C7/1006 , G11C7/22 , G11C8/16 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C2207/108
摘要： A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.
摘要翻译：信号对准电路包括多个焊盘，1比特1比特并行地接收输入信号; 第一传送单元，用于将输入信号作为与内部时钟的第一时钟信号同步的第一信号传送，并且将输入信号作为与内部时钟的第二时钟信号同步的第二信号传送; 第二传送单元，用于与所述内部时钟的第二时钟信号同步地传送所述第一信号; 以及对准单元，用于对准从第一和第二传送单元传送的第一和第二信号，并输出对准的信号作为输出信号。

7. 发明申请

US20100169583A1 MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE 有权
标题翻译：具有串行输入/输出接口的多端口存储器件
公开(公告)号：US20100169583A1
公开(公告)日：2010-07-01
申请号：US12717011
申请日：2010-03-03
申请人： Jin-Il Chung , Jae-II Kim , Chang-Ho Do , Hwang Hur
发明人： Jin-Il Chung , Jae-II Kim , Chang-Ho Do , Hwang Hur
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/222 , G11C8/16 , G11C29/26 , G11C29/32
摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.
摘要翻译：多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器集（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。测试I / O控制器与内部时钟同步输入/输出测试I / O信号。在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。

8. 发明申请

US20090290436A1 TEST CIRCUIT FOR MULTI-PORT MEMORY DEVICE 有权
标题翻译：多端口存储器件的测试电路
公开(公告)号：US20090290436A1
公开(公告)日：2009-11-26
申请号：US12474243
申请日：2009-05-28
申请人： Hwang Hur , Chang-Ho Do
发明人： Hwang Hur , Chang-Ho Do
IPC分类号： G11C8/16 , G06F12/00 , G11C7/10
CPC分类号： G11C29/26 , G11C8/16 , G11C11/401
摘要： A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode.
摘要翻译：半导体存储器件包括用于传送读取数据的读出总线; 用于传送写入数据的写入总线; 以及临时数据存储单元，连接在读总线和写总线之间，并由在测试模式期间启用的测试模式信号控制。

9. 发明授权

US07616022B2 Circuit and method for detecting skew of transistors in a semiconductor device 失效
标题翻译：用于检测半导体器件中的晶体管的偏斜的电路和方法
公开(公告)号：US07616022B2
公开(公告)日：2009-11-10
申请号：US11892584
申请日：2007-08-24
申请人： Hwang Hur , Jun-Gi Choi
发明人： Hwang Hur , Jun-Gi Choi
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G11C29/12005 , G11C2029/5002
摘要： A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation unit for reducing variation width of the linear voltage according to the performance of the transistor, a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage, and a comparison unit for comparing an output of the first attenuation unit and the saturation voltage.
摘要翻译：提供一种用于容易地检测半导体器件内的晶体管的偏斜的电路和方法。用于检测晶体管的偏斜的电路包括用于通过使用第一电源电压输出线性电压的线性电压产生单元，用于根据晶体管的性能减小线性电压的变化幅度的第一衰减单元，饱和电压产生单元，用于通过使用第二电源电压输出饱和电压;以及比较单元，用于比较第一衰减单元的输出和饱和电压。

10. 发明申请

US20090006912A1 Semiconductor memory device having burn-in test mode and method for driving the same 失效
标题翻译：具有老化测试模式的半导体存储器件及其驱动方法
公开(公告)号：US20090006912A1
公开(公告)日：2009-01-01
申请号：US12005445
申请日：2007-12-26
申请人： Hwang Hur
发明人： Hwang Hur
IPC分类号： G06F11/26 , G11C29/00
CPC分类号： G11C29/36 , G11C29/10 , G11C2029/3602
摘要： A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting controller configured to receive the first test control signal and the second test control signal to output a shifting control signal in response to the selection end signal; and a pattern test signal generator configured to select a stress pattern corresponding to the pattern selection signals to generate a plurality of test mode signals for controlling a sequential entry into a plurality of test modes for executing the stress pattern in response to the shifting control signal.
摘要翻译：半导体存储器件包括：模式选择器，被配置为响应于输入信号接收第一测试控制信号和第二测试控制信号以输出多个模式选择信号和选择结束信号; 移位控制器，被配置为接收第一测试控制信号和第二测试控制信号，以响应于选择结束信号输出移位控制信号; 以及模式测试信号发生器，被配置为选择与所述模式选择信号相对应的应力模式，以产生多个测试模式信号，用于响应于所述移位控制信号来控制顺序进入用于执行所述应力模式的多个测试模式。

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