专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150119253A1 METHOD FOR INCREASING THE INTEGRATION LEVEL OF SUPERCONDUCTING ELECTRONICS CIRCUITS, AND A RESULTING CIRCUIT 有权
标题翻译：提高超导电子电路集成度的方法和电路
公开(公告)号：US20150119253A1
公开(公告)日：2015-04-30
申请号：US14508514
申请日：2014-10-07
申请人： Hypres Inc.
发明人： Daniel Yohannes , Alexander F. Kirichenko , John Vivalda , Richard Hunt
IPC分类号： H01L39/22 , H01L39/02 , H01L27/18 , H01L39/24
CPC分类号： H01L39/223 , G11C11/44 , H01L27/18 , H01L39/025 , H01L39/2406 , H01L39/2493
摘要： A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.
摘要翻译：一种用于增加超导电子电路的积分电平的方法，包括制造由平坦化绝缘层隔开的图案化成布线的一系列平面化导电层，其中导电层之间连通通孔。与从底部向上的图案化的标准顺序相反，至少一个绝缘层中的通孔的图案在下面的导电层中的布线图案之前形成。这使得能够减少平坦化步骤的数量，导致更快更可靠的制造工艺。在优选实施例中，超导体是铌，绝缘体是二氧化硅。该方法可以在复杂集成电路中提供10个或更多个布线层，并且与布置在平坦化布线层上方的非平面化电路兼容。

2. 发明申请

US20170345990A1 METHOD FOR INCREASING THE INTEGRATION LEVEL OF SUPERCONDUCTING ELECTRONICS CIRCUITS, AND A RESULTING CIRCUIT 审中-公开
公开(公告)号：US20170345990A1
公开(公告)日：2017-11-30
申请号：US15679935
申请日：2017-08-17
申请人： Hypres, Inc.
发明人： Daniel Yohannes , Alexander F. Kirichenko , John Vivalda , Richard Hunt
IPC分类号： H01L39/22 , H01L27/18 , H01L39/02 , H01L39/24
CPC分类号： H01L39/223 , G11C11/44 , H01L27/18 , H01L39/025 , H01L39/2406 , H01L39/2493
摘要： A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

3. 发明授权

US10833243B1 System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits 有权
公开(公告)号：US10833243B1
公开(公告)日：2020-11-10
申请号：US15679789
申请日：2017-08-17
申请人： Hypres, Inc.
发明人： Sergey K. Tolpygo , Denis Amparo , Richard Hunt , John Vivalda , Daniel Yohannes
IPC分类号： H01L39/24 , H01L39/22 , H01L39/02
摘要： Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.

4. 发明授权

US10283694B2 Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit 有权
公开(公告)号：US10283694B2
公开(公告)日：2019-05-07
申请号：US15679935
申请日：2017-08-17
申请人： Hypres, Inc.
发明人： Daniel Yohannes , Alexander F. Kirichenko , John Vivalda , Richard Hunt
IPC分类号： H01L39/22 , H01L27/18 , H01L39/24 , H01L39/02 , G11C11/44
摘要： A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

5. 发明授权

US09741918B2 Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit 有权
公开(公告)号：US09741918B2
公开(公告)日：2017-08-22
申请号：US14508514
申请日：2014-10-07
申请人： Hypres Inc.
发明人： Daniel Yohannes , Alexander F. Kirichenko , John Vivalda , Richard Hunt
IPC分类号： H01L39/22 , H01L39/02 , H01L27/18 , H01L39/24
CPC分类号： H01L39/223 , G11C11/44 , H01L27/18 , H01L39/025 , H01L39/2406 , H01L39/2493
摘要： A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

6. 发明授权

US09130116B1 System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits 有权
标题翻译：用于为超导集成电路提供多导电层金属互连的系统和方法
公开(公告)号：US09130116B1
公开(公告)日：2015-09-08
申请号：US13887949
申请日：2013-05-06
申请人： Hypres Inc.
发明人： Sergey K. Tolpygo , Denis Amparo , Richard Hunt , John Vivalda , Daniel Yohannes
IPC分类号： H01L39/00 , H01L39/22 , H01L39/24
CPC分类号： H01L39/2493 , H01L23/48 , H01L27/18 , H01L39/025 , H01L39/223 , H01L2924/0002 , H01L2924/00011 , H01L2924/00
摘要： Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.
摘要翻译：超导集成电路需要多个布线层，以跨越电路分配偏置和信号，这些电路必须彼此交叉，有触点和不带触点。所有布线和触点必须是完全超导的，并且在现有技术中，每个布线层包括单个金属薄膜。公开了包括两种或更多种不同金属的连续层的替代布线层。这样的多金属布线层可以提供改善的杂质扩散阻力，更好的表面钝化和/或应力的减少，超过单金属布线层可达到的。所产生的过程导致包括多个约瑟夫逊结的集成电路中的边缘和产量得到改善。对于平面化和非平面化处理都公开了几个优选实施例。这些优选和其它方法可以应用于基于快速单通量量子逻辑的数字电路，以及使用约瑟夫逊结量子位的量子计算。

7. 发明授权

US08437818B1 System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits 有权
公开(公告)号：US08437818B1
公开(公告)日：2013-05-07
申请号：US13662490
申请日：2012-10-28
申请人： Hypres, Inc.
发明人： Sergey K. Tolpygo , Denis Amparo , Richard Hunt , John Vivalda , Daniel Yohannes
IPC分类号： H01L23/48 , H01L27/00
CPC分类号： H01L39/2493 , H01L23/48 , H01L27/18 , H01L39/025 , H01L39/223 , H01L2924/0002 , H01L2924/00011 , H01L2924/00
摘要： Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.

8. 发明授权

US09741920B1 System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits 有权
公开(公告)号：US09741920B1
公开(公告)日：2017-08-22
申请号：US14844866
申请日：2015-09-03
申请人： Hypres Inc.
发明人： Sergey K. Tolpygo , Denis Amparo , Richard Hunt , John Vivalda , Daniel Yohannes
IPC分类号： H01L39/24 , H01L39/02 , H01L39/22
CPC分类号： H01L39/2493 , H01L23/48 , H01L27/18 , H01L39/025 , H01L39/223 , H01L2924/0002 , H01L2924/00011 , H01L2924/00
摘要： Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式