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1. 发明申请

US20140054552A1 DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS 有权
标题翻译：超级电子产品加工制造双重屏蔽技术
公开(公告)号：US20140054552A1
公开(公告)日：2014-02-27
申请号：US13771330
申请日：2013-02-20
申请人： Hypres, Inc.
发明人： Sergey K. Tolpygo
IPC分类号： H01L39/02 , H01L39/24
CPC分类号： H01L27/18 , H01L39/025 , H01L39/12 , H01L39/223 , H01L39/2406 , H01L39/249 , H01L39/2493
摘要： An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
摘要翻译：基于使用双层光刻掩模对结点的侧壁和基极进行部分阳极氧化的改进的超导集成电路中约瑟夫森结的微细加工技术。掩模的顶层是抗蚀剂材料，并且底层是选择的电介质材料，以使抗蚀剂和下面的超导层之间的粘合力最大化，与下面的超导层进行蚀刻兼容，并且不溶于抗蚀剂，阳极氧化处理化学品。超导体优选是在二氧化硅层下的铌，其中常规的光致抗蚀剂或电子束抗蚀剂作为顶层。这种组合导致高密度超导集成电路的制造产量的显着增加，结点均匀性的增加和缺陷密度的降低。可以采用与微光刻相容的干蚀刻。

2. 发明申请

US20170179193A1 DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS 审中-公开
公开(公告)号：US20170179193A1
公开(公告)日：2017-06-22
申请号：US15456010
申请日：2017-03-10
申请人： Hypres, Inc.
发明人： Sergey K. Tolpygo
IPC分类号： H01L27/18 , H01L39/12 , H01L39/02 , H01L39/22 , H01L39/24
CPC分类号： H01L27/18 , H01L39/025 , H01L39/12 , H01L39/223 , H01L39/2406 , H01L39/249 , H01L39/2493
摘要： An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

3. 发明授权

US09741920B1 System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits 有权
公开(公告)号：US09741920B1
公开(公告)日：2017-08-22
申请号：US14844866
申请日：2015-09-03
申请人： Hypres Inc.
发明人： Sergey K. Tolpygo , Denis Amparo , Richard Hunt , John Vivalda , Daniel Yohannes
IPC分类号： H01L39/24 , H01L39/02 , H01L39/22
CPC分类号： H01L39/2493 , H01L23/48 , H01L27/18 , H01L39/025 , H01L39/223 , H01L2924/0002 , H01L2924/00011 , H01L2924/00
摘要： Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.

4. 发明授权

US09595656B2 Double-masking technique for increasing fabrication yield in superconducting electronics 有权
标题翻译：双屏蔽技术，用于提高超导电子产品的制造成本
公开(公告)号：US09595656B2
公开(公告)日：2017-03-14
申请号：US14850634
申请日：2015-09-10
申请人： Hypres Inc.
发明人： Sergey K. Tolpygo
IPC分类号： H01L29/06 , H01L39/24 , H01L39/02 , H01L39/12 , H01L39/22 , H01L27/18
CPC分类号： H01L27/18 , H01L39/025 , H01L39/12 , H01L39/223 , H01L39/2406 , H01L39/249 , H01L39/2493
摘要： An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
摘要翻译：基于使用双层光刻掩模对结点的侧壁和基极进行部分阳极氧化的改进的超导集成电路中约瑟夫森结的微细加工技术。掩模的顶层是抗蚀剂材料，并且底层是选择的电介质材料，以使抗蚀剂和下面的超导层之间的粘合力最大化，与下面的超导层进行蚀刻兼容，并且不溶于抗蚀剂，阳极氧化处理化学品。超导体优选是在二氧化硅层下的铌，其中常规的光致抗蚀剂或电子束抗蚀剂作为顶层。这种组合导致高密度超导集成电路的制造产量的显着增加，结点均匀性的增加和缺陷密度的降低。可以采用与微光刻相容的干蚀刻。

5. 发明授权

US09136457B2 Double-masking technique for increasing fabrication yield in superconducting electronics 有权
标题翻译：双屏蔽技术，用于提高超导电子产品的制造成本
公开(公告)号：US09136457B2
公开(公告)日：2015-09-15
申请号：US13771330
申请日：2013-02-20
申请人： Hypres, Inc.
发明人： Sergey K. Tolpygo
IPC分类号： H01L29/06 , H01L39/02 , H01L39/24
CPC分类号： H01L27/18 , H01L39/025 , H01L39/12 , H01L39/223 , H01L39/2406 , H01L39/249 , H01L39/2493
摘要： An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
摘要翻译：基于使用双层光刻掩模对结点的侧壁和基极进行部分阳极氧化的改进的超导集成电路中约瑟夫森结的微细加工技术。掩模的顶层是抗蚀剂材料，并且底层是选择的电介质材料，以使抗蚀剂和下面的超导层之间的粘合力最大化，与下面的超导层进行蚀刻兼容，并且不溶于抗蚀剂，阳极氧化处理化学品。超导体优选是在二氧化硅层下的铌，其中常规的光致抗蚀剂或电子束抗蚀剂作为顶层。这种组合导致高密度超导集成电路的制造产量的显着增加，结点均匀性的增加和缺陷密度的降低。可以采用与微光刻相容的干蚀刻。

6. 发明授权

US10833243B1 System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits 有权
公开(公告)号：US10833243B1
公开(公告)日：2020-11-10
申请号：US15679789
申请日：2017-08-17
申请人： Hypres, Inc.
发明人： Sergey K. Tolpygo , Denis Amparo , Richard Hunt , John Vivalda , Daniel Yohannes
IPC分类号： H01L39/24 , H01L39/22 , H01L39/02
摘要： Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.

7. 发明授权

US10109673B2 Double-masking technique for increasing fabrication yield in superconducting electronics 有权
公开(公告)号：US10109673B2
公开(公告)日：2018-10-23
申请号：US15456010
申请日：2017-03-10
申请人： Hypres, Inc.
发明人： Sergey K. Tolpygo
IPC分类号： H01L29/06 , H01L27/18 , H01L39/22 , H01L39/24 , H01L39/02 , H01L39/12
摘要： An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

8. 发明申请

US20150380632A1 DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS 审中-公开
公开(公告)号：US20150380632A1
公开(公告)日：2015-12-31
申请号：US14850634
申请日：2015-09-10
申请人： Hypres Inc.
发明人： Sergey K. Tolpygo
IPC分类号： H01L39/24 , H01L27/18 , H01L39/22 , H01L39/02 , H01L39/12
CPC分类号： H01L27/18 , H01L39/025 , H01L39/12 , H01L39/223 , H01L39/2406 , H01L39/249 , H01L39/2493
摘要： An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

9. 发明授权

US09130116B1 System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits 有权
标题翻译：用于为超导集成电路提供多导电层金属互连的系统和方法
公开(公告)号：US09130116B1
公开(公告)日：2015-09-08
申请号：US13887949
申请日：2013-05-06
申请人： Hypres Inc.
发明人： Sergey K. Tolpygo , Denis Amparo , Richard Hunt , John Vivalda , Daniel Yohannes
IPC分类号： H01L39/00 , H01L39/22 , H01L39/24
CPC分类号： H01L39/2493 , H01L23/48 , H01L27/18 , H01L39/025 , H01L39/223 , H01L2924/0002 , H01L2924/00011 , H01L2924/00
摘要： Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.
摘要翻译：超导集成电路需要多个布线层，以跨越电路分配偏置和信号，这些电路必须彼此交叉，有触点和不带触点。所有布线和触点必须是完全超导的，并且在现有技术中，每个布线层包括单个金属薄膜。公开了包括两种或更多种不同金属的连续层的替代布线层。这样的多金属布线层可以提供改善的杂质扩散阻力，更好的表面钝化和/或应力的减少，超过单金属布线层可达到的。所产生的过程导致包括多个约瑟夫逊结的集成电路中的边缘和产量得到改善。对于平面化和非平面化处理都公开了几个优选实施例。这些优选和其它方法可以应用于基于快速单通量量子逻辑的数字电路，以及使用约瑟夫逊结量子位的量子计算。

10. 发明授权

US08437818B1 System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits 有权
公开(公告)号：US08437818B1
公开(公告)日：2013-05-07
申请号：US13662490
申请日：2012-10-28
申请人： Hypres, Inc.
发明人： Sergey K. Tolpygo , Denis Amparo , Richard Hunt , John Vivalda , Daniel Yohannes
IPC分类号： H01L23/48 , H01L27/00
CPC分类号： H01L39/2493 , H01L23/48 , H01L27/18 , H01L39/025 , H01L39/223 , H01L2924/0002 , H01L2924/00011 , H01L2924/00
摘要： Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.

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